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DESIGNING UART BY USING GATE-LEVEL IMPLEMENTATION
Iffah binti Mohamed@Mohamad Saim
Bachelor of Engineering with Honours
(Electronics and Computer Engineering)
2006
DESIGNING UART BY USING GATE-LEVEL
IMPLEMENTATION
Encik Norhuzaimin Julai
Nama Penyelia
Sg. Merab Luar, 43650 Bandar Baru
Bangi, Selangor
IFFAH BINTI MOHAMED@MOHAMAD SAIM
(HURUF BESAR)
Lot 6057, Desa Shafeeqah,
UNIVERSITI MALAYSIA SARAWAK
BORANG PENGESAHAN STATUS TESIS
Judul:
__________________________________________________________________________
SESI PENGAJIAN: 2005/2006
Saya _____________________________________________________________________________
mengaku membenarkan tesis * ini disimpan di Pusat Khidmat Maklumat Akademik, Universiti Malaysia Sarawak dengan syarat-syarat kegunaan seperti berikut:
1. Tesis adalah hakmilik Universiti Malaysia Sarawak. 2. Pusat Khidmat Maklumat Akademik, Universiti Malaysia Sarawak dibenarkan membuat salinan
untuk tujuan pengajian sahaja.
3. Membuat pendigitan untuk membangunkan Pangkalan Data Kandungan Tempatan. 4. Pusat Khidmat Maklumat Akademik, Universiti Malaysia Sarawak dibenarkan membuat salinan
tesis ini sebagai bahan pertukaran antara institusi pengajian tinggi.
5. ** Sila tandakan ( √ ) di kotak yang berkenaan
SULIT (Mengandungi maklumat yang berdarjah keselamatan atau kepentingan Malaysia seperti yang termaktub di dalam AKTA RAHSIA RASMI 1972).
TERHAD (Mengandungi maklumat TERHAD yang telah ditentukan oleh organisasi/badan di mana penyelidikan dijalankan).
TIDAK TERHAD
Disahkan oleh
_______________________________ ____________________________________
(TANDATANGAN PENULIS) (TANDATANGAN PENYELIA)
Alamat tetap: __________________________
_____________________________________ ____________________________________
_____________________________________
Tarikh: ____________________________________ Tarikh: _____________________________
CATATAN * Tesis dimaksudkan sebagai tesis bagi Ijazah Doktor Falsafah, Sarjana dan Sarjana Muda.
** Jika tesis ini SULIT atau TERHAD, sila lampirkan surat daripada pihak berkuasa/organisasi berkenaan dengan menyatakan sekali sebab dan tempoh tesis ini
perlu dikelaskan sebagai SULIT atau TERHAD.
R13a
This Final Year Project attached here:
Title : Designing UART by Using Gate-Level Implementation
Student Name : Iffah binti Mohamed@Mohamad Saim
Matric No : 8308
has been read and approved by:
Mr. Norhuzaimin Julai Date
(Supervisor)
DESIGNING UART BY USING GATE-LEVEL IMPLEMENTATION
IFFAH BINTI MOHAMED@MOHAMAD SAIM
This report is submitted in partial fulfillment of the requirement for the degree
of Bachelor of Engineering with Honours
(Electronics and Computer Engineering)
Faculty of Engineering
UNIVERSITI MALYSIA SARAWAK
2006
ii
To my mother and father
with love.
iii
ACKNOWLEDGEMENT
Praises to Lord for His blessing this project managed to complete successfully on
time. Next, I would like to express my deepest appreciation to my first supervisor, Mr.
Norhuzaimin Julai for his guidance and support thorough out the project. My
appreciation also goes to my second supervisor, Ms. Sakena Abdul Jabar. Special thanks
to Ms. Maimun binti Huja Husin that help me every time I have encountered problems. I
would like to dedicate this project to my beloved parents, family, friends and loves one
for their continuous support and advices. Lastly, many thanks go to all lecturer, staff and
technician of Faculty of Engineering for their contributions directly or indirectly towards
this project.
iv
ABSTRAK
Universal Asynchronous Receiver/Transmitter (UART) sangat terkenal di antara
peralatan komunikasi sesiri terutamanya di kalangan peralatan yang dipisahkan oleh
jarak yang jauh. UART mengandungi dua litar utama iaitu penghantar di mana ianya
menghantar data secara selari kepada sesiri dan penerima yang menerima data secara
sesiri kepada selari. Tujuan utama projek ini adalah mereka model penuh UART
menggunakan perlaksanaan aras get. Perisian yang digunakan ialah Altera MAX+PLUS
II di mana ianya mudah disesuaikan mengikut rekaan yang diingini. Tugas pertama
ialah mereka laluan kawalan yang turut dikenali sebagai Finite State Machine (FSM)
dan laluan data bagi modul penghantar dan penerima. Persamaan Boolean yang
diperolehi melalui pemetaan Peta Karnaugh diperlukan untuk pengurangan penggunaan
get logik di dalam litar FSM. Seterusnya ruang data, ruang perpindahan, penghasil
kesamaan dan pemeriksa kesalahan direka menggunakan gabungan dan susanan logik
rekaan. Tugas terakhir ialah menggabungkan kedua-dua modul membentuk rekaan
UART penuh. Beberapa ujian dan analisis dijalankan ke atas data yang dihantar dan
diterima, kesalahan kesamaan, kesalahan framing dan kesalahan overrun untuk
memastikan setiap komponen berfungsi dengan baik.
v
ABSTRACT
Universal Asynchronous Receiver/Transmitter (UART) is very popular among
serial communication devices especially between devices that are separated by long
distances. The UART consists of two main circuits which is a transmitter, that transmits
parallel-to-serial data and a receiver which is receives serial-to-parallel data. The main
purpose of this project is to design a full UART module by using gate-level
implementation. The software used is Altera MAX+PLUS II and it is easily adapted to
specific design needs. The first task is to design a control path also known as Finite State
Machine (FSM) and data path for Transmitter and Receiver Module. Boolean equations
has been derived from Karnaugh Map are needed to minimize the usage of logic gate in
the FSM circuit. Then Data Register, Shift Register, Parity Generator and Error Checker
for both modules are designed by using combinational and sequential logic design. The
final task is to combine both modules as a full UART design. Some tests and analysis
had been done on transmitted and received data, parity error, framing error and overrun
error to ensure that each component is working properly.
vi
TABLE OF CONTENTS
Page
ACKNOWLEDGEMENT iii
ABSTRAK iv
ABSTRACT v
TABLE OF CONTENTS vi
ABBREVIATION xi
LIST OF FIGURES xiii
LIST OF TABLES xvii
Chapter
1. INTRODUCTION 1
1.1 Universal Asynchronous Receiver Transmitter 1
1.2 Importance of UART 4
1.3 Gate-Level Implementation 4
1.4 MAX+PLUS II 5
1.5 Project Objectives 5
1.6 Project Scope 6
vii
1.7 Report Overview 6
2. LITERATURE REVIEW 5
2.1 Serial Transmission 8
2.1.1 Synchronous Transmission 9
2.1.2 Asynchronous Transmission 10
2.2 Implementation of UART Using Gate-Level 12
2.3 UART Standard Serial Data Format 14
2.4 UART Operation 15
2.5 UART Module 16
2.5.1 Transmitter Module 19
2.5.2 Receiver Module 20
2.6 UART Block Diagram 21
2.6.1 Shift Register 22
2.6.2 Data Register 23
2.6.3 Parity Generator 24
2.6.4 Error Checker 25
3. METHODOLOGY 27
3.1 UART Transmitter 27
3.1.1 Data Path 28
3.1.2 Control Path 29
3.1.2.1 UART Transmitter State Diagram 30
3.1.2.2 State Table 32
viii
3.2 UART Receiver 34
3.2.1 Data Path 35
3.2.2 Control Path 36
3.2.2.1 State Diagram 36
3.2.2.2 State Table 41
3.3 Combination of Transmitter Module and Receiver Module 43
3.3.1 UART Data Path 44
3.3.2 UART State Diagram 45
3.4 Gate-Level Implementation 46
3.4.1 Data Register 46
3.7 Shift Register 48
3.5 The Equation and K Maps for the Control Signals 48
3.5.1 For Transmitter Module 48
3.5.2 For Receiver Module 51
3.6 Simulation 54
4. RESULTS AND DISCUSSION 55
4.1 Transmitter Module 55
4.1.1 Transmitter Control Unit Check 56
4.1.2 TDR Check 56
4.1.3 TSR Check 58
4.1.4 Parity Generator Check 61
4.1.5 Transmitter Check 62
ix
4.2 Receiver Module 63
4.2.1 Receiver Control Unit Check 63
4.2.2 RSR Check 64
4.2.3 Overrun and RDR Check 65
4.2.4 Parity Generator Check 68
4.2.5 Parity and Framing Error Check 69
4.2.6 Latch Data 73
4.3 Receiver Check and Verification 74
4.3.1 Receiver Check 75
4.3.2 Data Verification 76
4.3.3 Parity Error Verification 78
4.3.4 Framing Error Verification 79
4.3.4.1 One Bit 79
4.3.4.2 Start Bit 80
4.3.4.3 Stop Bit 81
4.3.4.4 Overrun Error Verification 82
4.4 Combination of Transmitter and Receiver Module 84
5. CONCLUSION AND RECOMMENDATIONS 86
5.1 Project Objectives 86
5.2 Project Scope 87
5.2.1 ALTERA MAX+PLUS II 87
5.3 Problems 87
x
5.4 Recommendation 88
5.5 Conclusion 89
REFERENCES 90
BIBLIOGRAPHY 93
APPENDIX 95
A 95
B 102
C 113
D 115
xi
ABBREVIATION
AHDL - Altera Hardware Description Language
CPU - Central Processing Unit
HDL - Hardware Description Language
FE - Framing Error
FPGA - Field Programmable Gate Array
FSM - Finite State Machine
K-Map - Karnaugh Map
LSB - Least Significant Bit
MSB - Most Significant Bit
OE - Overrun Error
PC - Personal Computer
PE - Parity Error
PGT - Positive Going Transition
RDR - Receive Data Register
RSR - Receive Shift Register
RX - Receiver
RXRDY - Receive Data Ready
SIN - Serial Input Data
xii
TDR - Transmit Data Register
TSR - Transmit Shift Register
TX - Transmitter
TXRDY - Transmit Data Ready
UART - Universal Asynchronous Receiver Transmitter
USART - Universal Synchronous-Asynchronous Receiver Transmitter
VHDL - Very High Description Language
VLSI - Very Large Scale Integrated circuit
xiii
LIST OF FIGURES
Page
1. Figure 1.1 Example of UART 3
2. Figure 2.1 Example of serial transmission 9
3. Figure 2.2 Synchronous Transmission 10
4. Figure 2.3 Asynchronous Transmission 12
5. Figure 2.4 Standard Serial Data Format 14
6. Figure 2.5 UART Serial Transmission 16
7. Figure 2.6 UART Module 16
8. Figure 2.7 Transmitter Module 19
9. Figure 2.8 Sequence of transmitter 20
10. Figure 2.9 Receiver Module 20
11. Figure 2.10 Data format 21
12. Figure 2.11 Sequence of receiver 21
13. Figure 2.12 UART Block Diagram 22
14. Figure 2.13 Shift Register Application 23
15. Figure 2.14 Parity Generator 24
16. Figure 2.15 Error Checker 26
xiv
17. Figure 3.1 UART Transmitter Module 28
18. Figure 3.2 UART Transmitter Data Path 29
19. Figure 3.3 UART Transmitter Control Path 29
20. Figure 3.4 Transmitter State Diagram 30
21. Figure 3.5 UART Receiver Module 34
22. Figure 3.6 UART Receiver Data Path 35
23. Figure 3.7 UART Receiver Control Path 36
24. Figure 3.8 Receiver State Diagram 37
25. Figure 3.9 UART Module 43
26. Figure 3.10 UART Data Path 44
27. Figure 3.11 UART State Diagram 45
28. Figure 3.12 D-type Latch 46
29. Figure 3.13 Data Register 47
30. Figure 3.14 Shift Register 48
31. Figure 4.1 Transmitter Control Unit Output 56
32. Figure 4.2 TDR_LD and TDR_EN are high 57
33. Figure 4.3 TDR_LD is low while TDR_EN is high 57
34. Figure 4.4 TDR_EN is low while TDR_LD is high 57
35. Figure 4.5 TDR_LD and TDR_EN are low 58
36. Figure 4.6 Both TSR_LD and TSR_EN are low and then high 59
37. Figure 4.7 TSR_LD is low 59
38. Figure 4.8 TSR_EN is low 60
39. Figure 4.9 TSR_LD and TSR_EN are low 60
xv
40. Figure 4.10 TSR_LD and TSR_EN with no low input at the
beginning of the clock cycle
61
41. Figure 4.11 Parity Generator Check 61
42. Figure 4.12 UART Transmitter 62
43. Figure 4.13 Receiver Control Unit Output 63
44. Figure 4.14 RSR_LD and RSR_EN are high 64
45. Figure 4.15 RSR_LD and RSR_EN are low 64
46. Figure 4.16 RSR_LD is low while RSR_EN is high 65
47. Figure 4.17 RSR_EN is low while RSR_LD is high 65
48. Figure 4.18 OE is high while RXRDY1 is low 66
49. Figure 4.19 OE and RXRDY is high 66
50. Figure 4.20 RDR_LD and RDR_EN are high 67
51. Figure 4.21 RDR_LD, RDR_EN and RXRDY1 are high 67
52. Figure 4.22 RDR_EN is low while RDR_LD is high 68
53. Figure 4.23 RDR_LD is low while RDR_EN is high 68
54. Figure 4.24 Parity Generator Check 69
55. Figure 4.25 Parity and Framing Error Check 70
56. Figure 4.26 Incorrect ONE bit 70
57. Figure 4.27 Incorrect STOP bit 71
58. Figure 4.28 Incorrect START bit 71
59. Figure 4.29 Incorrect PARITY bit 72
60. Figure 4.30 Incorrect parity bit generated 72
61. Figure 4.31 Data latch 73
xvi
62. Figure 4.32 Parity Error is inserted 73
63. Figure 4.33 Overrun is inserted 74
64. Figure 4.34 Framing Error is inserted 74
65. Figure 4.35 UART Receiver 75
66. Figure 4.36 Original data 76
67. Figure 4.37 Adjusted data, from 00000011 to 00000010 77
68. Figure 4.38 Adjusted parity from ‘0’ to ‘1’ 77
69. Figure 4.39 Original parity 78
70. Figure 4.40 Adjusted parity from ‘0’ to ‘1’ 78
71. Figure 4.41 Original data 79
72. Figure 4.42 Adjusted One bit from ‘1’ to ‘0’ 80
73. Figure 4.43 Original data 80
74. Figure 4.44 Adjusted Start bit from ‘0’ to ‘1’ 81
75. Figure 4.45 Original data 81
76. Figure 4.46 Adjusted Stop bit from ‘1’ to ‘0’ 82
77. Figure 4.47 No Overrun Error 83
78. Figure 4.48 Adjusted RX_RDY 83
79. Figure 4.49 Overrun Error is high 84
80. Figure 4.50 Full UART output 85
xvii
LIST OF TABLE
Page
1. Table 2.1 Data obtained from gate-level simulation of the UART
core
13
2. Table 2.2 Cell Format Sequences of the bit stream 14
3. Table 2.3 I/O Functions of the UART Module 18
4. Table 2.4 Error Checks 25
5. Table 3.1 Transmitter State Table 33
6. Table 3.2 Data Shifting States 39
7. Table 3.3 Receiver State Table 42
8. Table 3.4 Truth Table of D-type Latch 47
ABBREVIATION
AHDL - Altera Hardware Description Language
CPU - Central Processing Unit
HDL - Hardware Description Language
FE - Framing Error
FPGA - Field Programmable Gate Array
FSM - Finite State Machine
K-Map - Karnaugh Map
LSB - Least Significant Bit
MSB - Most Significant Bit
OE - Overrun Error
PC - Personal Computer
PE - Parity Error
PGT - Positive Going Transition
RDR - Receive Data Register
RSR - Receive Shift Register
RX - Receiver
RXRDY - Receive Data Ready
SIN - Serial Input Data
TDR - Transmit Data Register
TSR - Transmit Shift Register
TX - Transmitter
TXRDY - Transmit Data Ready
UART - Universal Asynchronous Receiver Transmitter
USART - Universal Synchronous-Asynchronous Receiver Transmitter
VHDL - Very High Description Language
VLSI - Very Large Scale Integrated circuit
1
CHAPTER 1
INTRODUCTION
1.1 Universal Asynchronous Receiver Transmitter
Universal Asynchronous Receiver Transmitter (UART) is the main component of
the serial communication between two devices. UART accepts bytes of data from the
Central Processing Unit (CPU) 8 bits at a time in parallel and then transmits back the
data in serial, one bit at a time to the data’s destination. Another UART will assemble
the bits into complete bytes simultaneously.
This serial transmission is widely used with modems and non-networked
communication between computers, terminals and other devices. There two types of
serial transmission, which are synchronous and asynchronous.
2
UART consists of one receiver module and transmitter module. The transmitter
performs parallel-to-serial conversion on the 8-bit data received from the CPU, while the
receiver performs serial-to-parallel conversion on the asynchronous data frame received
from the serial input data (SIN). To ensure integrity and the synchronization of
asynchronous serial data, Start, Parity and Stop bits are added to the serial data.
The first device will converts bytes into bits (incoming parallel information to
serial data), while the other device will converts back the bits into bytes (serial-to-
parallel conversion). In order to synchronize the asynchronous serial data and to insure
the data integrity, Start, Parity and Stop bits are added into the serial data [1].
Data is transferred one byte to the receiver using the format as shown in Figure 1.1.
The transmission character is composed of an 8-bit data byte, sent Least Significant Bit
(LSB) first, preceded by a start bit (LOW) and followed by a stop bit (HIGH). When no
character is being transmitted, the line is idle (HIGH). The line need not go idle between
characters, as it is possible for the start bit of a transmission to immediately follow the
stop bit of the previous transmission [2].
The UART also has control capability and a processor interrupt system that can be
adjusted to minimize software management of the communications link.