Performance Analysis of Vertical Strained-SiGe Impact Ionization MOSFET Incorporating Dielectric Pocket (VESIMOS-DP)

Ismail Saad1, Zuhir Hamzah

1*, Bun Seng

1, Khairul Anuar

1, Bablu Ghosh

1, Nurmin Bolong

1, Razali Ismail

2

1 Nano Engineering & Material (NEMs) Research Group, School of Engineering & IT, Universiti Malaysia Sabah, 88999,

Kota Kinabalu, Sabah 2 Computational Nanoelectronics (CONE) Research Group, Faculty of Electrical Engineering, Universiti Teknologi

Malaysia, Skudai 81310, Malaysia

*email: ismail_s@ums.edu.my / zuhirhamzah@yahoo.com

Abstract— The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. The comparison between VESIMOS and VESIMOS-DP was done to show the advantages of incorporating dielectric pocket (DP) to the performance of the device. An improved stability of threshold voltage, VTH was found for VESIMOS-DP device of various DP size ranging from 20nm to 80nm. The stability is due to the reducing charge sharing effects between source and drain region. However, the presence of DP layer has introduced another potential barrier in addition to the delta p+ (δp+) triangular potential barrier. Thus, increased amount of gate voltage needed to overcome those barriers and allows the electrons to flow from source to drain. Moreover, the DP layer has suppressed the parasitic bipolar transistor effect (PBT) with higher breakdown voltage as compared to without DP layer. Hence, the incorporation of DP into VESIMOS has enhanced its performance and presents elevated characteristics for nano-electronics device.

Keywords- IMOS, Dielectric Pocket, VESIMOS, VESIMOS-DP, Parasitic Bipolar Effects, nano-electronics

I. INTRODUCTION Among the phenomenon faced by the Complementary

Metal Oxide Semiconductor (CMOS) is the limitation of subthreshold swing due to drain-induced barrier lowering (DIBL) effect. Subthreshold swing for CMOS is also limited to 60 mV/dec at room temperature [1-2]. In order to reduce the subthreshold swing even further, a device that work on the principle of impact ionization MOSFETs (IMOS) has been developed successfully [3-5]. The device showed good subthreshold slopes at 10 mV/dec and better ION/IOFF current ratio. However, this lateral IMOS needs a high supply voltage (VDS) and suffer from degradation caused by hot carrier effects. Hence, causing reliability issues [6-7].

To counter this effect, the vertical concept of IMOS which is planar-doped barrier MOSFET with a floating body (PDBFET) was developed and investigated. [8-9]. It shows excellent subthreshold slope of 4 mV/dec and suppress leakage current efficiently at high temp as well as a very good ION/IOFF current ratio. Most importantly, it showed no hot carrier effects [10-11]. Hence, it was reliable. The device also shows capability of working properly under high temperatures. However, it need high VDS in order to achieve

the desired device characteristics and suffers a remarkable hysteresis.

Still there was an opportunity to bring down the supply voltages further down. Hence, the concept of strained Silicon Germanium (SiGe) in the vertical IMOS device was developed [12-13]. It showed both reduction in threshold voltage and supply voltage of about 0.7V. This compressive strain developed results in high carrier mobility, high impact ionization rates and better ON-OFF current ratios, besides retaining the good subthreshold slopes shown by vertical IMOS devices [14-15].

However, this device suffers low breakdown voltage and parasitic bipolar transistors (PBT) effect. At high drain voltages (> 2.5V), the gate loses its control over the drain current due to sufficiently higher impact ionization rates at the gate channel. The npn structure acts as a bipolar transistor with floating base causing parasitic bipolar transistors (PBT) effect [16]. Hence to obtain low threshold voltages at relatively lower supply voltages and suppressing the effect of PBT in getting higher breakdown voltage, dielectric pocket (DP) is incorporated into Vertical Strained-SiGe Impact Ionization MOSFET.

This paper presents the effect of incorporating dielectric pocket (DP) into Vertical Strained-SiGe Impact Ionization MOSFET (VESIMOS-DP) to the performance of the device. DP concept was proposed as an alternative to the pocket ion implantation concept in order to overcome short channel effects (SCE) in conventional MOSFET [17-18]. The vicinity of DP near the drain region has introduced another potential barrier and thus increased gate to source voltage is needed for electrons to flow. However, it has reduces charge sharing effects associated with the source and thus improves threshold voltage stability. In addition, the DP layer has suppressed the parasitic bipolar transistor effect (PBT) with higher breakdown voltage as compared to without DP layer.

II. DEVICE STRUCTURE The Vertical Strained Silicon Germanium (SiGe) Impact

Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) is based on a gated triangular barrier diode (TBD). A highly doped delta p+ layer sandwiched with intrinsic channel region between n+ doped source and drain with the addition of SiGe and DP layer called TBD because of its triangular

2013 Fifth International Conference on Computational Intelligence, Modelling and Simulation

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DOI 10.1109/CIMSim.2013.66

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2013 Fifth International Conference on Computational Intelligence, Modelling and Simulation

2166-8531/13 $26.00 © 2013 IEEE

DOI 10.1109/CIMSim.2013.66

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shaped potential barrier. A transistor fabricated with a highly doped δp+ layer in an intrinsic channel region is also known as planar-doped barrier MOSFET (PDBFET).

The advantage of this device is the arbitrary choice of doping levels necessary to obtain a significant potential barrier. The high doping of the delta layer which creates a large potential barrier makes it possible to achieve high electric fields in the intrinsic zone near the drain without applying a very high VDS [15]. A positive gate source voltage, VGS is necessary to lower the barrier and allow the electron flow from source to drain forming a significant ON current of the device. Careful selection of the delta layer thickness is recommended to have a good subthreshold slope. Hence, an optimum value of delta layer thickness and doping was chosen in this device in order to obtain desired subthreshold slopes.

Figure 1 shows the detailed cross-sections of the Vertical Strained-SiGe Impact Ionization MOSFET with dielectric pocket (VESIMOS-DP) using Sentaurus package for performance analysis [19]. This structure comprises an n+ doped source and drain region, an intrinsic channel containing a highly doped δp+ layer (Boron = 4x1019/cm3) and two sided gates. The intrinsic-Si, i-Si regions which sandwich the p+ delta layer helps to reduce the lateral electric field near source and drain [20]. Thus, an optimum thickness of i-Si region is needed so that they could effectively reduce the lateral electric fields. The presence of i-Si regions between highly doped S/D regions has also reduced the impurity scattering.

Figure 1. VESIMOS-DP device structure with respective layer thickness of source, drain, δp+, i- Si, SiGe (Ge=30%), Si-cap and DP.

The strained SiGe layer thickness was 20nm with Ge=30%. The DP layer thickness was also 20nm. However, the DP layer thickness was varied to examine its effects towards device performance. The DP layer was also sandwiched with intrinsic Silicon caps with 5nm thickness. This Si-cap acts the same function as i-Si to improve the stability of the overall device.

The Source was n-doped with Antimony with a doping concentration of 2.08x1018 /cm3. The Drain was also n-doped with Phosphorus with a doping concentration of 2.08x1018 /cm3. The high doped S/D doping was chosen as the device concept was based on impact ionization. VESIMOS-DP is an impact ionization device with drift current mechanism, which requires high electric fields. Both the drift current and the electric fields depend on the doping concentrations. Hence, high doping concentrations are crucial for obtaining better device characteristics.

III. DEVICE CONCEPT VESIMOS-DP shows three distinguish operating modes;

conventional MOSFET, Impact Ionization (II) and Bipolar (BJT) mode. In conventional MOSFET mode, low VDS and insufficient electric field limits the II rate. The barrier is lowered by VGS and an electron channel is formed below the gate between i-Si and δp+ region. As the VDS rise, the electric field in the drain side intrinsic region increased until the impact ionization rate occurs in the drain side intrinsic zone. The device is now in the II mode. The potential barrier is lowered by VGS, thus allows the electron travel from the source into the drain region.

In this II mode, a significant lower subthreshold swing value is obtained due to the extremely fast rising current in the subthreshold region. This current amplification is not caused by the impact ionization rate like in lateral IMOS. Instead, the holes generated by the II accumulated in the δp+ layer region charged the body of the transistor and causing a dynamic reduction of threshold voltage, VTH during switched ON operation. Hence, a very good subthreshold and ION/IOFF ratio value is obtained in this mode.

The impact ionization rate is depends on the electric field in the drain side intrinsic region. Increasing the VDS will increase the II rate exponentially. This leads to the rising hole current at the δp+ layer region. At a point when the δp+ layer region cannot contain with the surge of holes currents, the gate loses its control over the drain current. The third operating mode is initialize which is parasitic bipolar (BJT) mode. In this mode, the n+ drain region act as a collector, the n+ source region as an emitter and δp+ layer as a base as depicted in figure 1.

As the drain source current (IDS) increase, the holes generated by II in the δp+ region also increases which act as a base current. This will initiate the ON current of the device same like the Bipolar Junction Transistor (BJT) operation as depicted in Figure 2. A small current entering the base is amplified to produce a large collector and emitter current. When there is a positive potential difference measured from the emitter of an NPN transistor to its base as well as from the base to the collector, the transistor becomes active.

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Figure 2. Parasitic Bipolar Transistor (PBT) effect principle of VESIMOS-DP device in Bipolar (BJT) mode.

In this ON state, current flows between the collector and emitter of the transistor. Most of the current is carried by electrons moving from emitter to collector as a minority carriers in the P-type base region. Although even lower subthreshold swing value is obtained, a significant hysteresis is observed in the input characteristic at this operating mode. When the VDS in the δp+ layer region exceed certain level, the device can no longer be switched OFF. This is called Parasitic Bipolar Transistor (PBT) effect. To counteract this effect, VDS has to be reduced below the level necessary for impact ionization to occur or apply a negative VGS in order to switch OFF the device again [9]. The introduction of DP also can minimize the infiltration of the minority carrier towards drain region. Hence, reduce the PBT effect.

IV. DEVICE SIMULATION The electrical characteristics of the device were done by

solving Poisson’s equation and continuity equation numerically within the defined meshes of the device [21]. The electrical potential energy and electron band structure can be computed using Poisson’s equation. Poisson’s equation relates variations in electrostatic potential to local charge densities and is given by equation 1.

ρϕε −=∇ )(div (1)

Where, φ is the electrostatic potential, ε is the local permittivity and ρ is the local space charge density, which is the sum of fixed charges like electrons, holes and ionized impurities. Continuity equations are then used to calculate the current densities of the electrons and holes. Continuity equations describe the electron and hole densities that evolve from transport processes and generation-recombination processes which is given by equation 2 and 3 respectively.

nnn RGJdivqt

n −+=∂∂ →1

(2)

ppp RGJdivqt

p −+=∂∂ →1

(3)

Where →→

pn JJ & is Electron and hole current densities,

pn GG & is Electron and hole generation rates,

pn RR & is Electron and hole recombination rates and q is electronic charge. Boltzmann transport framework is used to solve these two equations. The relationship between the current density of electrons and holes and carrier concentration exhibited during this self-consistent process. Transport process is derived from fundamental equations. The transport model used in this simulation is drift-diffusion model and is given by equation 4 and 5.

][, nL

nnnnn qkTDnqDEqnJ μμ =∇+=

→→ (4)

][, pL

ppppp qkTDpqDEqpJ μμ =∇+=

→→ (5)

Where →→

pn JJ & is Electron and hole current densities,

pn μμ & is electron and hole mobility, pn DD & is electron

and hole diffusivity, TL is lattice temperature, k is Boltzmann constant and q is charge. The drift–diffusion (DD) transport model with the Boltzmann carrier transport framework was used to predict the I–V characteristics of DG-MOSFET [22]. Even for nanoscale size > 10 nm, Granzneretal [23] have shown that for DG-MOSFET’s current characteristics, the DD and Monte-Carlo simulation results produced excellent agreement. While Ren and Lundstorm [24] and Rhew and Lundstorm [25] have revealed that the DD model can predict I–V characteristics of short-channel MOS devices more realistically than the energy-balance (EB) model.

Impact ionization model of carrier generation mechanism has been employed in this study. II occurs in a sufficiently high electric field, under which the free carriers gain sufficient amount of energy to undergo collision with other free carriers and generate electron-hole pairs (EHP). When the generation rate of the free carriers is high enough, it would result in avalanche breakdown. The impact ionization model employed in this research study was Selberherr’s [26] impact ionization models, which is a local impact ionization model. The general II process can be described by the equation 6.

ppnn JJG αα += (6)

Where, nα & pα

is ionization coefficients and nJ & pJ

is electron and hole current densities. Selberherr’s model is recommended for most cases of device simulation.

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V. RESULT AND DISCUSSION The transfer characteristic is examined by biasing the

drain voltage, VDS and ramp the VGS at defined bias steps. Figure 3 shows the comparison of transfer characteristic, IDS-VGS of VESIMOS-DP with different DP thickness.

Figure 3. Transfer Characteristics, IDS-VGS of VESIMOS-DP for Si0.7Ge0.3, S/D doping =2.0x1018/cm3, VDS=1.75V.

Figure 3 revealed that VESIMOS-DP works well for low VDS, which has overcome the problem faced by the conventional IMOS devices [8-10]. The energy of electrons required in the impact-ionization region is much lower compared to the lateral IMOS since the impact ionization is not the only mechanism contributing to the extremely fast rising drain current. Instead, the holes generated by the II accumulate in the δp+ layer region will charged the body of the transistor and causing a dynamic reduction of threshold voltage during the switched ON.

Threshold voltage, VTH was found to be stable across various DP size from 20nm to 80nm. There is slightly higher VTH obtained for 80nm DP (VTH =1.362V) as it require more energy to pass through higher potential barrier compared to the others. This stable VTH =1.35V obtained due to the vicinity of DP layer near the drain end has reduce charge sharing between the source and drain. Subthreshold voltage is in direct proportion to the leakage currents. Hence, a lower subthreshold voltage ensures low leakage currents. A very low leakage current is obtained in the VESIMOS-DP as the triangular potential barrier excellently suppresses current flow from source to drain. Together with the ON currents near 1mA, a very good ION/IOFF ratio of about 1011 is obtained in this device.

The slight different and consistency of VESIMOS-DP subthreshold value (S = 19 mV/dec) has given advantages for incorporating DP layer near the drain end. This subthreshold voltage obtained is much lower than the conventional MOSFET limit which is 60 mV/decade due to the impact ionization mechanism of VESIMOS-DP device. This analysis can be summarized in Table 1, which shows the comparison of threshold voltage and subthreshold

voltage obtained for VESIMOS-DP device with different DP size.

TABLE I. VESIMOS-DP VTH and S at different modes of

operation

DP Size (nm) 20nm 40nm 60nm 80nm

VTH (V) 1.35 1.352 1.356 1.362

S (mV/decade) 19.5 19.2 19.0 19.1 From table 1, it can be computed that DP with 60nm size

has superb performance as it has lowest subthreshold value, S=19.0 mV/decade and lower threshold voltage, VTH =1.356V when compared to others. Figure 4 shows the comparison of transfer characteristics, IDS-VGS between VESIMOS-DP and VESIMOS without DP layer.

Figure 4. Transfer Characteristics, IDS-VGS of VESIMOS-DP and VESIMOS without DP for Si0.7Ge0.3, VDS=1.75V.

By using a linear extrapolation of transconductance (gm) to zero, a VTH of 0.87V was obtained with a VDS of 1.75V. The VTH obtained is found to be 48% lower than the VESIMOS-DP as the presence of DP layer has introduced another potential barrier in addition to the δp+ triangular potential barrier. Thus, a higher amount of VGS is needed to lowering both barriers and allows the electron to move from source to drain.

At off-state mode, drain leakage current, IOFF is independent to the gate voltage, but increases with the increasing drain voltage as depicted in Figure 4. A very low off-state leakage current, IOFF = 7.3x10-17 A/μm and good drive current, ION = 1.5x10-10 A/μm taken at VDS = 1.75 V was explicitly shown in VESIMOS-DP device. Hence, the device have good switching characteristics because of high ION/IOFF ratio which approximately 10-6 for VESIMOS-DP and 10-11 for VESIMOS respectively. This is due to the triangular barrier concept which effectively keeps the leakage current low.

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In addition, the output characteristic was also highlighted a very good drain current at different gate voltage with the increasing of drain voltage as shown in figure 5. It was happen due to the existence of strain SiGe at the channel region has enhanced the carrier transport in the VESIMOS-DP channel.

Figure 5. Output characteristics of VESIMOS-DP device at different gate voltage.

It can be seen from figure 5 that initially the drain current rises sharply and then increases gradually before going into breakdown state. The sharp rise in drain current can be attributed to the presence of Ge. Germanium has high and symmetric impact ionization rates (αN ≈ αP), which ensures that the transition from OFF state to the ON state is abrupt [5].

For VGS > 1.80V, the device instead of going to the bipolar mode as in VESIMOS, it undergoes breakdown. In bipolar mode, the n+ source region acts as emitter, the n+ drain acts as collector and δp+ layer as a base as illustrated in the figure 1. The holes generated by impact ionization acts as a base currents and drain source current increases as the current of the parasitic bipolar transistor (PBT) is switched on. This additional current amplification mechanism contributes to the lower subthreshold slope, but with a certain hysteresis [10] due to the PBT effect.

However, with the presence of DP layer at the drain side region, the PBT effect has been suppressed for VDS ≤ 2.5V. For VDS > 2.5V, the PBT effect has been minimized to a minimum level as the δp+ layer cannot contain with the surge of holes current due to higher II rate. Nevertheless, most of the device application operation voltage is below 2.5V which merit the incorporation of DP layer into the device.

Figure 6. Comparison of output characteristics between VESIMOS and VESIMOS-DP device at VGS=1.75V (Impact Ionization mode)

Figure 6 shows the Comparison of output characteristics between VESIMOS and VESIMOS-DP device taken at VGS=1.75V which is in the Impact Ionization mode. It can be seen that the VESIMOS has lower breakdown voltage compared to VESIMOS-DP which is about 2.8V and 3.6V respectively. It may be attributed by the low bandgap of the Ge compared to other semiconductor materials [27]. It is also the inherent properties of Germanium (Ge) which has breakdown strength two times lower than the Si. The results can be summarized in Table 2, which shows the comparison of threshold voltage, subthreshold voltage, breakdown voltage, BV and ION/IOFF ratio obtained for both VESIMOS and VESIMOS-DP respectively.

TABLE II. VESIMOS and VESIMOS-DP VTH and S at

different modes of operation

Parameter No DP DP

VTH (V) 0.87 1.35

S (mV/decade) 17.8 19.0

BV (V) 2.8 3.6

ION/IOFF 10-11 10-6

All simulated data was validated with the experimental

data in order to verify the accuracy of the simulation work. As no experimental data was available for Vertical SiGe IMOS, the vertical Si IMOS data was used [8]. It can be observed that the simulated data is synchronous with the experimental data and is in close approximation of 0 to 5% range as shown in figure 7

Breakdown Region

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Figure 7. Validation of simulated data with experimental data (Abelein et.al.,2007) of Si vertical IMOS device.

VI. CONCLUSION The mechanism of incorporating dielectric pocket (DP)

that leads to the electrical behavior of the Vertical Strained-SiGe Impact Ionization MOSFET towards the performance of the device has been investigated and explained. The dependency of the DP size and Ge Molar concentration on the device performance is shown using Sentaurus TCAD tools. Due to the DP layer, threshold voltage, VTH was found to be stable across various DP size from 20nm to 80nm. The threshold voltage, VTH obtained is found to be 48% lower than the VESIMOS as the presence of DP layer has introduced another potential barrier in addition to the δp+ triangular potential barrier. VESIMOS-DP has a very low off-state leakage current, IOFF = 1x10-16 A/μm and good drive current, ION = 1x10-5 A/μm taken at VDS = 1.75 V with excellent ION/IOFF ratio of about 1011. Moreover, the DP layer has suppressed the parasitic bipolar transistor effect with higher breakdown voltage as compared to without DP layer.

ACKNOWLEDGMENT The authors would like to acknowledge the financial

support from ERGS (ERGS0002-TK-1/2011) fund of MOHE and E-Science fund (03-01-10-SF0175) of MOSTI Malaysia. The author is thankful to the University Malaysia Sabah (UMS) for providing excellent research environment in which to complete this work.

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