RSM2011 Proc., 2011, Kota Kinabalu, Malaysia

Investigation on Effect of Tilt Angle Ion

Implantations for Vertical Double Gate

MOSFET

Abu Bakar A.R, Ismail Saad School of Engineering & I.T

Universiti Malaysia Sabah(UMS)

Kota-Kinabalu, Sabah, Malaysia

Email: abubakar.abdrahman@gmail.com, ismail_s@ums.edu.my

Abstract- The significance of variation on tilt angle ion

implantation for fabricating the Vertical MOSFET with ORI

(Oblique Rotating Implantation) technique is investigated. For

this purpose, the angle of the ion implantation for forming the

source and drain region is varied from 0° to 80°. Various effects

on physical structure of the device and its corresponding

electrical properties have been observed. The overall result

promotes the optimal angle for the ion implantation of the

Vertical Double Gate MOSFET (VDGM) structure is found to be

remarkable at 45° with shorter channel length, Lg= 45nm, lower

sheet resistance RD= 14.7Ω, RS=28.9 Ω, high sub-threshold swing,

SS= 62mV/dec and high saturation current, IDSAT= 1.04mA/µm.

I. INTRODUCTION

Over the past few decades, miniaturization in silicon

integrated circuit technology has progressed substantially as

following the Moore’s Law with exponential growth in the

number of transistor being packed into a microchip [1].

Undoubtedly, the key factor needs to be considered in order to

increase the packing density in a microchip is by scaling down

the channel length of the MOSFET. Nevertheless, the scaling

technology of the conventional planar MOSFET is typically

most reliable down to 50nm [7]. In order to overcome this

limit the vertical MOSFET arrangement was introduced

[2,3,4]. Among merits had gained for such device includes

high drive current, reduces short channel effect, shorter

channel, increase packing density, ballistic transconductance,

sub-threshold voltage swing increases, multiple gate, etc.

However, the two most common approaches for fabricating

vertical MOSFET that are epitaxial deposition and

implantation of dopant are known prone to inherit problems

such as non-self aligned channels which lead to various

problems such as high threshold voltage, high DIBL, high

leakage current and low drive ON current [4]. Hence, the

oblique rotating ion implantation (ORI) technique had been

introduced in [4] and proven to capable of producing a self-

aligned symmetrical source/drain region and formation of

sharp vertical channel over the silicon pillar. In this paper,

similar device arrangement as presented in [2,4,5] is

investigated further. In previous work, the tilt angle during ion

implantation for forming the S/D junction only fixed at 45°.

The work presented here examines the effect of varying the tilt

angle during ion implantation process which ranged from 0° to

80° angles. Various physical and electrical characteristics are

observed as presented in section II and III. The TCAD

software packages from Silvaco namely Athena and Atlas

have been utilized for the device fabrication and the

characterization process.

II. DEVICE PHYSICAL STRUCTURE AND PROFILE

The cross-sectional of vertical double gate MOSFET

(VDGM) with various tilt angle ion implantation process for

creating the dual source and common drain region is

illustrated in Fig. 1. The source regions are placed on both

bottom side of the pillar while the drain region implanted on

the top. The fabrication process started with selection of a p-

type silicon highly doped with boron (1019 cm-3) for creating

the base body/ substrate of the VDGM. The dry etching

technique is performed to create a pillar structure with a height

of 222nm to accommodate a symmetrical dual gate device.

The Nitride and thin oxide relief are deposited on all of the

surface and anisotropic etching performed to create spacer

about 970nm thickness for active area formation. The FILOX

layer with 60nm thickness is grown on the surfaces of the

region that targeted for the source and drain to reduce the

parasitic effect [2]. Subsequently, the implantation of the S/D

region is taken place.

Fig. 1, Cross-sectional of vertical double gate MOSFET with various

angle ion implantation process (angle range =from 0° to 80°).

DRAIN

FILOX FILOX

FILOX

SOURCE 1 SOURCE 2

GATE

1

GATE

2

CHANNEL

CHANNEL

θ =

80°

θ =

80°

θ = 0°

100 978-1-61284-846-4/11/$26.00 ©2011 IEEE

RSM2011 Proc., 2011, Kota Kinabalu, Malaysia

By utilizing the ORI technique (the fabrication process

explained in detail as in [4]) , Arsenic with a dose of 105 cm-3

and energy of 150keV implanted initially at zero degree and

then the wafer is rotated about y-axis at 180° to form two

identical source regions. Then, a Polysilicon doped with n+

Phosphorus (5x10-19cm-3) is deposited on a thin oxidation

layer about 3nm thickness and anisotropic dry etched to leave

the gate contact (200nm) on both side wall of the pillar. In this

paper, the process is explored further with variations in tilt

angles (0° to 80°) implantation. Only five significant tilt

angles cases is selected and presented here. The Fig. 2 (a) and

(b) reveals the physical structure of the VDGM that have been

developed through ORI method with tilt angle of minimum at

0°and maximum at 80° respectively.

Tilt

angle,

θ

Measured

Channel

Length,

Lg (nm)

Source-to-

Source

width, tsi

(nm)

Junction Depth, Xj

(nm)

Sheet

Resistance, Rsheet

(Ω/sq)

Source Drain Source Drain

0° 55 220 195 199 9.7 9.2

25° 60 180 143 153 14.8 10.4

45° 45 138 107 129 28.9 14.7

65° 65 146 65 87 119.7 52.4

80° 190 233 31 56 1658.5 167.6

From Table I, it is discovered that although exactly the

same amount of Arsenic concentrations (6x1015 cm-3) and

energy (150keV) is used for the junction implantation process,

the fabricated device exhibits very much different structure

with highly dependent to the tilt angle. In general, it can be

seen that, both of the region are narrowing as angle is

increases. In fact, beyond the angle of 80° the source junction

is not fully formed with very shallow in depth measured only

31nm. Moreover, the sheet resistance for the source region

becomes enormously large (1658.5 Ω/sq) and far from

acceptable value for the transistor purpose (25 Ω/sq). The

SIMS vertical profile for the various angle implantations is

illustrated in Fig. 3. It is noted that, the 0° implantation

produces highly constant Arsenic measured at 6.8x1018 cm-3 in

the body region while at 25° the concentration is reduced to

the lowest at 5.4x1014 cm-3.

In Fig.4 and Fig. 5 shows a trend where as the implantation

angle approaching 45° the higher concentration of electron

and hole obtained in the source region of the device. The most

significant effect found in 80° device, where the amount of the

concentration abruptly dropped by a factor of 2. This can be

clarified by the extremely shallow area on both of the source

regions as illustrated in Fig. 2(b).

Fig. 2, (a) 0 degree VDGM and (b) 80 degree VDGM

TABLE I

PHYSICAL CHARACTERISTICS OF VDGM WITH VARIOUS ANGLE OF S/D

IMPLANTATION

Fig. 3, SIMS vertical doping profile source/body/source for 0°,25°,45°,60°

and 80°respectively.

Fig. 4, Electron Concentration for 0°,25°,45°,60° and 80°respectively.

Fig. 5, Hole Concentration for 0°,25°,45°,60° and 80°respectively.

(a) (b)

Gate1 Gate2

So

urc

e1

So

urc

e2

Drain

Body

Gate1 Gate2

So

urc

e1

So

urc

e2

Drain

Body

Poly PolyPolyPoly

Ch1

Ch2

Ch1 Ch2

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RSM2011 Proc., 2011, Kota Kinabalu, Malaysia

III. DEVICE ELETRICAL CHARACTERISTICS

As referring to Table II, it is clearly shown that, most of the

implantation angle capable of achieving nearly ideal

60mV/dec sub-threshold swing [10]. However, it has a limit,

when the implantation angle approaching 80° then, the device

performance deteriorates indicated by an increase of sub-

threshold voltage to 97mV/dec as shown in Fig. 7. The higher

sub-threshold swing voltage is desirable to be avoided in order

to obtain a higher switching speed response ON/OFF or logic

HIGH/LOW transitions [9].

Tilt angle, θ Vth(V)

@Vds 25mV

SS(mV/dec)

0° 0.71 64

25° 0.74 68

45° 0.72 62

65° 0.67 63

80° 1.56 97

The device implanted at 80° is having highest threshold

voltage rated at 1.56V for VDS=25mV as shown in Fig. 6. This

result has a good agreement with the impaired structure as

depicted in Fig. 2(b). Moreover, the device fabricated beyond

this angle will suffer from shallow junction and high sheet

resistance problem. This will degrade the carrier mobility on

the source/drain. Hence, only little amount of current can be

flowing along the channel. It is also noted, the threshold

voltage for 65° shows a tremendous improvement which rated

a 0.67V. On the other hand, the 65° device owing the high

leakage current rate at close to 10-12A/µm, while the 80°

device shows small leakage below 10-16A/µm. This can be

explained by the body doping concentration where in 80°

device most of the region dominated by the silicon doped with

boron which reflects to high concentration of hole (Fig. 5).

Thus, the potential barrier to create path for the leakage

current to flow from drain to source at VGS=0V with electron

as the carrier correspondingly will be high [8].

From the output characteristic as depicted in Fig. 8, it is

revealed that, the implantation at 45° shows better

performance. For given VGS=2.0V at VDS=1.5V, the 45°

device can produce the highest saturation current

IDS=1.04mA/µm. Although the 65° device having excellent

threshold voltage, the 45° device outperforms it mainly due to

longer channel length in 65°. For the device of 0°,25° and 80°

have prevails lower output current due to all of these device

sharing L-shape channel problem which will degrade the

current flowing performance as referred in [6]. The L-shape

distract the flowing of the current carrier as opposed to 45°

and 65° device where the channel in the form of purely

vertical shape.

IV. CONCLUSION

The effect of angle variation during ion implantation

process for forming the source/drain region on VDGM

structure has revealed few significant aspects. The prominent

result of varying the angle during implantation process shown

the depth of source and drain becomes shallow as angle is

approaching higher degree. This has led the sheet resistance

becoming extremely high particularly for the case of 80°

where the value is reaching 1.7kΩ. Almost all angle capable

of fabricating high swing close to 60mV/dec but 80° is the

Fig. 6, Transfer Characteristics for 0°,25°,45°,60° and 80°respectively. Fig. 7, Transfer Characteristics for 0°,25°,45°,60° and 80°respectively.

Fig. 8, Transfer Characteristics for 0°,25°,45°,60° and 80°respectively.

TABLE II

ELECTRICAL PROPERTIES OF VDGM WITH VARIOUS ANGLE S/D

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RSM2011 Proc., 2011, Kota Kinabalu, Malaysia

limit. Although 65° implantation produces low threshold

voltage, it has severe limitation with having the highest OFF

state leakage current. From overall performance it has

revealed that the optimal angle is 45°. Among the advantages

obtained are low sheet resistance, shorter channel length, high

carrier concentration, high sub-threshold swing and high

saturation current.

ACKNOWLEDGMENT

I would like to express my sincere appreciation and thankful

to my supervisor Dr. Ismail Saad for his support for me to

undertaking of this project and to the School of Engineering &

I.T, UMS for providing such a good facilities.

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