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Nanowire Conductance Biosensor by Spacer Patterning Lithography Technique for DNA Hybridization Detection: Design and Fabrication Method

Uda Hashim, Shahrir Salleh, Emi Azri Shohini, Siti Fatimah Abd Rahman

Nano BioChip Research Group School of Microelectronic Engineering, Universiti Malaysia Perlis (UniMAP)

01000 Kangar, Perlis, Malaysia. uda@unimap.edu.my

Abstract

The use of Silicon nanowires has allowed the introduction of many new signal transduction technologies in biosensors. The sensitivity and performance of biosensors is being improved by using doping process for their construction. This research presents the design and fabrication of a Silicon nanowire for deoxyribonucleic acid (DNA) hybridization detection using electrodes made of nanowires whose width is comparable to the size of a DNA molecule. During hybridization, DNA change from single stranded DNA (ssDNA) to double stranded DNA (dsDNA) cause the change of charge density of molecules structure. Fabrication of a Silicon nanowire (NW) using spacer patterning lithography (SPL) techniques is addressed and characterization of its conductivity altogether with capacitance effect is discussed in this research.

Key words: Nanowire, DNA hybridization, Biosensor, Spacer Patterning Lithography.

1. Introduction

Nanotechnology can be defined as the development and use of devices that have a characteristic size of only a few nanometers. The ultimate goal is to fabricate devices that have every atom in the right place. Such technology would give the opportunity to minimize the size of a device and to reduce the material, energy and time necessary to perform its task. Over the past few years, the field of microelectronic has seen a rapid increase in both the number and diversity of "Biochips" - devices used to detect objects of biological interest, ranging from small molecules to microorganisms. DNA is a biological component of particular interest to researchers because of its importance in drug development, detection of pathogens, genetic screening, and genome sequencing. The ultimate goal of researchers is to develop a suitable base requires a base that can interact individually, requiring a detector of a similar size [1]. One feature of DNA sensors that could make both goals attainable is the utilization of a transduction mechanism that is nano-scale and can be easily integrated with CMOS technology. The small dimensions of such devices would produce dense device arrays with each sensor capable of detecting very low concentrations of a target DNA molecule. CMOS compatibility would allow these devices to incorporate with modern high-speed analog and digital circuits capable of rapid transcription and analysis of binding events [2]. We

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present the fabrication and characterization of a device that is CMOS compatible and utilizes a nano-scale transduction mechanism for the detection of DNA.

1.1 Operation Principle

The operation principle of the sensor is as follows. Any tiny size sample like DNA should be bound ligand with an absorbed receptor on the Si nanowires. When molecules are fixed between them, it can change the charge carrier density of the wires. This change of charge carrier density results in an effective change of conductance by time that can be monitored electronically. The sensor structure allows for direct conversion of molecular recognition and binding events to electronic signals. [3]

! lL-__ --'

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Figure 1: Operation principle of nanowirejilledwith DNA

1.2 Biosensor

A biosensor is a device for the detection of an analyte that combines a biological component with a physicochemical detector component.ill It consists of 3 parts: 16 the sensitive biological element (biological material (eg. tissue, microorganisms,

organelles, cell receptors, enzymes, antibodies, nucleic acids, etc), a biologically derived material or biomimic) The sensitive elements can be created by biological engmeenng.

16 the transducer or the detector element (works in a physicochemical way; optical, piezoelectric, electrochemical, etc.) that transforms the signal resulting from the interaction of the analyte with the biological element into another signal (i.e., transducers) that can be more easily measured and quantified;

16 associated electronics or signal processors that is primarily responsible for the display of the results in a user-friendly way.

Biomolecular properties have usually been examined using biosensors as small as the molecular sizes, fabricated by electron-beam (EB) lithography [6]. However, this technique is very expensive due to its low throughput. In this study we present parallel processes for nano-size pattern generation on a wafer scale with resolution comparable to the best electron beam lithography. The technique is based on the conformal deposition of a thin-film material by plasma enhance chemical vapor deposition (PECVD) over a previously patterned step in a sacrificial material. The sacrificial layer can then be removed selectively, leaving only the material deposited (spacer) on the sidewall with its dimension comparable to desired nano-size. Then, the spacer must be removed completely leaving the pair sidewall as the next mask for the wire formation.

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2. Starting Material

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The starting material used in this project is a p-type, 100 mm in diameter (4 inch wafer) silicon-on-insulator (SOl) wafer. Reported benefits of SOl technology relative to conventional silicon (bulk CMOS) processing include: .@S Lower parasitic capacitance due to isolation from the bulk silicon, which improves

power consumption at matched performance . .@S Resistance to latchup due to complete isolation of the n- and p- well structures.

From a manufacturing perspective, SOl substrates are compatible with most conventional fab processes. In general, an SOl-based process may be implemented without special equipment or significant retooling of an existing laboratory. The primary barrier to SOl implementation is the drastic increase in substrate cost, which contributes an estimated 10-15% increase to total manufacturing costs.

3. Mask Specification and Layout Design

As for the lithography process, three photomask are employed to fabricate the nanowire using conventional photolithography technique. Commercial Chrome mask is expected to be used in this research for better photomasking process. Mask 1 is used to develop the sidewall, Mask 2 is used for the gold pad and Mask 3 is for the test channel. The photomask is designed using AutoCAD and then printed onto a chrome glass surface.

4. Process Fabrication Development

The fabrication of nanowire in this research uses the Spacer Patterning Lithography (SPL) method which is low-cost and compatible to standard CMOS fabrication process. Spacer patterning lithography coupled with anisotropic etching using ICP-RIE is the two main processes used in this experiment to fabricate this silicon nanowire. Electrical properties of silicon nanowire are then controlled by choosing a silicon substrate with an intended dopant type and concentration.

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4.1 Spacer Patterning Lithography

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The process begins with deposition 200-500 nm layer of silicon oxide (Si02) as the sacrificial layer on a clean highly doped SOl wafer following by the first mask pattern on top of it. This Si02 and Si3N4 are deposited by Plasmalab 80 plus Compact Plasma System by Oxford Instruments, plasma enhance will deposit the Si02 layer before making the proper mask alignment on top of it. The conditions are 700 sccm N20, 150 sccm Ar, 1000 mT pressure, 30Watt power and 150°C temperature for Si02. After deposition, photo resist (PR) solution will be loaded onto the Si02 layer before making the proper mask alignment on top of the PRo By using MIDAS exposure system (by applying UV light through a mask), pattern from the first mask is transferred on the PRo Buffered Oxide Etch (BOE) can be used to remove the silicon oxide layer but in this case, vertical profile is needed, so dry etch is the choice to etch the silicon oxide layer. Prior to this, development and etching process using SAMCO ICP-RIE inductive coupled plasma - reactive ion etching at 2.5nm S-l, the pattern layer is finally moved onto the Si02 layers. The conditions are 50 sccm CF4, 30 sccm Ar, 250V bias, 800Watt ICP power and 5 Pa pressure. This recipe etched produced vertical sidewall profile with an angle 82°_88°. The residue PR is then removed using the Plasma-PreenII-862 system by Plasmatic Systems Inc. Then, a thin layer about IOOnm-200nm of Silicon Nitride (Si3N4) is deposited on top of it. The conditions are 60 sccm Ar, 285 sccm N2, 600mT pressure, 25Watt power and 150°C temperature.

Std Rate High Rate Std Rate Std Rate Std Rate Step 1 2 3 Oxide Oxide Nitride SiO.Ny A-Si

Recipe Recipe Recipe Recipe Recipe Step Name Pump Purge Surface Clean Deposition Deposition Deposition Deposition Deposition Gas - 5% SiH.1 Ar (seem) - - - 150 450 60 450 500 Gas - N20 (sccm) - - - 700 700 - 700 -

Gas - NH3 (seem) - - - - - - - -

Gas - N2 (sccm) - 400 GOO - - 285 - -

Pressure (mT) - 1000 650 1000 500 GOO 1000 1500 Power HF 0fI/) at 13.56MHz - - 20 30 30 25 15 20 Temperature °C 150 150 150 150 150 150 150 200 Time (minutes) 5 5 1

Deposition rate (nm/minute) - - - 58 105.8 26 50nm (est) 25 Refractive Index - - - 1.45 1.45 2.02 N.A. Uniformity - - - <±5% <±5% <±5% <±5% <±5%

Table 1: Plasma Enchanced Chemical Vapour Deposition (PECVD) Process Recipes

Material Recipe CF4 CHF3 SF6 02 Ar Bias ICP Power APC/Control(Pa) Silicon 5 30 0 0 28 0 300 500 5.00 Silicon Nitride 13 0 12 0 0 30 250 800 5.00 Silicon Oxynitride 20 0 12 0 0 30 250 800 1.00 Silicon Oxynitride 14 0 12 0 0 30 250 800 8.00 Silicon Oxide (Thin) 15 50 0 0 0 30 250 800 5.00 Silicon Oxide (Thick) 6 50 0 0 0 30 300 800 5.00 Si Resist P.Step 1 22 10 15 0 0 10 250 800 5.00 Si Resist P.Step 2 - 0 0 0 20 0 30 200 1.00 Remove Resist only - 0 0 0 20 0 30 200 1.00 Poli Silicon 18 0 0 50 0 30 250 650 4.00 Amorphous Silicon 19 50 0 0 0 30 300 500-700 5.00 Minimum Etching Effect - 50 0 0 0 30 50 - 5.00

Table 2: 1CP-RlE Process Recipes

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UV LIGHT DRY ETCH

.0.0.0.0 ������

I--------tj > I i> • Photomask • Photoresist D Silicon D Silicon Oxide D Silicon Nitride

Figure 2: Layer by layer alignment and patterning method

This thin layer of Silicon Nitride (ShN4) is deposited uniformly onto the SOl to create the layer for spacer formation (the main process of the SPL technique). The spacer is then defined using ICP-RIE etching by removing the silicon oxide. The spacer formed will be the next mask for the highly doped crystalline silicon substrate. The nanowire is then defined using ICP-RIE etching by removing the silicon. This process is the critical step on fabrication process, since it determines the nanowire size and dimension.

DRY ETCH

a.--������� ������ DRY ETCH

I----------ti > i i > D Silicon D Silicon Oxide D Silicon Nitride

DRY ETCH

n

Figure 3: Layer by layer alignment and patterning method

4.2 Gold Pad Contact Formation

-

• Photoresist

• SIlicon N�rlde

• Amophous Silicon

o Burled Oxide

o Silicon

o AUrum ( Gold)

Figure -I: Process flow of gold pad

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Prior characterization and electrical testing, contact point is formed by deposition of aurum (gold) material prior to the fabricated nanowire. Gold is used to have a good reliability via contact and it has a very good conductivity. This is to ensure the device has a good electron flow and no bias effect to the sensing nanowire.

A layer of 500nm thick of Aurum is deposited using E-beam Evaporator onto the surface of the fabricated nanowire. The layer is then coated and patterned using photolithography process to form the contact point. Aqua Regia is used for etching. Finally, the photoresist layer is removed to expose the gold pad for contact.

4.3 Test Channel Formation

-

• Photoresist

• Silicon Nitride

• Amophous Silicon

o Burled Oxide

o Silicon

o Aurum ( Gold I

-

Figure 5: Si3N.J passivation layer process flow

Figure 5 shows the fabrication of the Si3N4 passivation layer which uses the Si3N4 to isolate the testing area and the electrical contact point. Starting with the deposition of the ShN4 using Plasma Enhanced Chemical Vapor Deposition (PECVD), a layer of Si3N4 is deposited on the surface of the nanowire and the gold pad. Then, a photoresist is coated and patterned using photolithography process. Inductively Coupled Plasma Reactive-Ion­Etching (ICP-RIE) is used to etch the ShN4 between the patterns and exposed the nanowire area for DNA sample drop and contact point. Finally, the photoresist layer is removed to form the Si3N4 passivation layer.

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5. DNA preparation and Testing

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There are two types of sample needs to be prepared and tested in this experiment.

5.1 DNA Sample preparation

Figure 6: DNA sample

Preparation of 2 sample known as separate ds-DNA (Probe DNA) and various unknown ss-DNA (Target DNA). The Probe DNA is a known reference sample DNA for testing the unidentified Target DNA. The mixture of these 2 DNA will hybridize or not is known earlier for testing purpose or offline sensor testing.

5.2 DNA Hybridization Test

Analyte (Target DNA)

Recognition layer (Probe DNA)

Signal

Nanowire

Figure 7: Signal identification

,

???

??1 IDENTIFICATION

..... _- -- -

..... , /

.,

The process of identification starts with the Probe DNA is denatured by heat or chemical denaturant and placed in solution or on a solid substrate, forming a reference segment. Then, a various unknown ss-DNA (Target DNA) is prepared. Unknown DNA sample is introduced to the reference segment. The complement of the reference segment will hybridize to it. This concentration must be suitable to the size of nanowire area. Identification of electrical form is counter measured to test the sample and conclude the result. The semiconductor parameter analyzer (SPA) system is used to characterize the conductivity of the nanowire. Spectrum analyzer (SA) is used to manipulate the output signal and easier identification process.

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5.3 Detection of DNA hybridization.

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A DNA molecule is positioned on the nanowires by electrostatic trapping from a dilute aqueous buffer containing about one molecule per area (1 00 nml This technique was developed for the trapping of single molecules, and has been shown to be successful for a variety of nanoparticles.

. .

. . .

. . .

/ fI[j�����

Gold

Buried Oxide

Silicon Substrate

Figure 4: Pad to pad measurement of different nanowire pattern using spectrum analyzer / semiconductor parameter analyzer

We began by investigating some of our contact pads, which we fabricated on silicon on insulator wafer, using a two-tier measurement procedure. In this procedure, the reference plane of the first-tier calibration was placed in the first pad, as described above. The reference plane of the second-tier calibration was located at the second contact pads fabricated on the silicon substrate. The signal line of this nanowire fabricated in the second level of metal (metal 2), and its ground plane was fabricated in the first level of metal (metal 1 ). This allowed us to directly measure the scattering parameters of the contact pads we had fabricated on the silicon wafer. This investigation showed that the electrical parasitics of the contact pads fabricated on the silicon wafer were dominated by their shunt capacitance and conductance.

6. Results and Discussions

The Si02 etched produced vertical sidewall profile with an angle 82°_88°. The resulting pattern sidewall profile is observed by scanning electron microscope (SEM) after dry etching is not ideally vertical, showing some broadening for smaller spacers «50 nm) and a noticeable undercut for larger spacers (>50 nm). The length of nanowire absolutely depends on width of spacer.

Figure 8: Image of sidewall and spacer formation under SEM

Figure 9 shows cross-sectional SEM photographs of the nanowire. The concave shape of cross-sectional nanowire is due to the shape of spacer especially at the top and the middle. Only small part a bottom shows as planar surface. The height of the wires were

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not perfectly the same because of the Si layer is over etched and it is not easy to confirm the height of two separating layer while etching.

'-'H �1 • LZ .. )) �1 · .. ,� ,. tt.', . ) . .

Figure 9: Nanowire image under High Power Microscope and 3-D model.

Characterization and optimization of the fabricated nanowire is the crucial steps in the development of this biosensor. It's extremely important to produce the perfect nanowire at the nano-scale resolution and edible for transmission of a single electron. The sensitivity of the sensors depends strongly on the width of the wires which results the detection of DNA hybridization changes responsively.

SUMMARY

'"

ss� ... unknown 55-DNA

(Target DNA)

il SIG)lAl. .. .. . . ... s a .. ta

.. 0."

hybridization

Figure 10: Sensor characteristic changes

Sublithographic nanowire was fabricated by spacer lithography. We showed an example application of these techniques. Experiments show the nanowire conductive conductor can be fabricated by spacer lithography and used for the detection of DNA hybridization without labeling. DNA hybridization was detected by conductance measurements, and the conductance was found to decrease as input frequency decreases when hybridization occurs. Due to the full compatibility with silicon microfabrication technology, DNA chips without any requirement of labeling process are thus practical which can be capable of cost reduction and dramatically speed up evaluation of DNA hybridization.

Acknowledgement

The authors wish to thank Universiti Malaysia Perlis (UniMAP), Ministry of Science, Technology & Innovation (MOST!) and Ministry of Higher Education for giving the opportunities to do this research in the Micro & Nano Fabrication Cleanroom. The appreciation also goes to all the team members in the Microelectronic & Nanotechnology Group especially in the Nano Biochip Research Group.

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Biographical notes:

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Uda Hashim received his PhD in Microelectronic from Universiti Kebangsaan Malaysia (UKM) in 2000. He is a Professor and Director of the Institute of Nanoelectronic Engineering in Universiti Malaysia Perlis (UniMAP), Malaysia. He is the core researcher of microelectronics & nanoteclmology cluster and also the team leader in the UniMAP Nano­Biochip Research Group. His current research interest includes Research Managements, Nanoelectronics, Biochips, E-Beam Lithography, Photolithography, Nano-structure

fonnation.. Semiconductor processing, CMOS process and devices. He has produced more than 30 academic papers in journals as well as conference proceedings worldwide in nanotechnology especially in nanoelectronics related field of research.

REFERENCES

Muhamad Emi Azri Shohini and Shahrir Salleh are postgraduate student in the School of Microelectronic Engineering at Universiti Malaysia Perlis (UniMAP), Malaysia. TIley are also the researcher of the UniMAP Nano-Biochip Research Group. They received their Bachelors degree in Material Physics and Mechatronics Eng from UTM in 2006. TIleir current post-graduate researches are the nanogap and nanowire biosensor for DNA hybridization detection.

[ 1 ] Arnoldus Jan Storm, Delft University Press, pp. 1-2,2004. [2] Y. Okahata, T. Kobayashi, K. Tanaka, and M. Shimomura, American Chemical Society, 120, pp. 6165, 1998. [3] http://en.wikipedia.orglwikilBiosensor [4] International Union of Pure and Applied Chemistry. "biosensor". Compendium of Chemical Terminology Internet edition. [5] Umasankar Yogeswaran and Shen-Ming Chen, 21 January 2008, A Review on the Electrochemical Sensors and Biosensors Composed of Nanowires as Sensing Material [6] Uda Hashim, Muhamad Emi Azri Shohini. 2007. Theoritical and Experimental Study Towards Fabrication of Nanogap Dielectric Biosensor Reversed Spacer Lithography. Proceeding International Conference on Advanced Materials and Nanotechnology, Langkawi Kedah. pp. 57. [7] Muhamad Emi Azri Shohini and Uda Hashim. Nanogap Gold Electrodes by Spacer

Lithography for DNA Hybridization Detection. Proceeding Malaysian Technical Universities Conferences on Engineering and Technology. Vol. 2. pp. 292-295. March 8-10 2008, Kangar, Perlis.

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