A 6-10.6 GHz CMOS PA with Common-Gate as an Input Stage for UWB Transmitters

S.A.Z Murad and M.M Shahimim School of Microelectronic Engineering Universiti Malaysia Perlis (UniMAP)

P.O Box 77, d/a Pejabat Pos Besar 01000 Kangar, Perlis, Malaysia

sohiful@unimap.edu.my

R.K Pokharel, H. Kanaya and K. Yoshida Graduate School of Information Sciences and Electrical

Engineering, Kyushu University Fukuoka, 819-0395 Japan

murad@yossvr3.ed.kyushu-u.ac.jp

Abstract— The design of a 6.0-10.6 GHz UWB CMOS power amplifier (PA) for ultra-wideband (UWB) transmitters in TSMC 0.18-µm CMOS technology is presented. The UWB PA proposed in this paper employing a common gate (CG) amplifier as the input stage for wideband matching and the current-reused technique is used to save the power consumption and to enhance gain at the higher frequency. The shunt peaking inductors were used to improve gain flatness and to increase the total bandwidth of the circuit. The post-layout simulation results show that the input return loss (S11) was less than -8 dB, output return loss (S22) was less than -10 dBm, and average gain was approximately 11 dB over the frequencies ranges of interest. The input and output 1-dB compression point is -12 dBm and 0 dBm, respectively. Moreover, an excellent phase linearity property (group delay) of ±55.8 ps across the whole band was obtained with power consumption of 18 mW. The chip area is 0.77 mm².

Keywords- power amplifier; ultra-wideband; common-gate; current-reused; phase linearity

I. INTRODUCTION UWB systems have attracted a great deal of interest to

many researchers due to their potential for high-speed wireless communications. Approved by Federal Communication Commission (FCC), the UWB technology using the unlicensed 3.1-10.6 GHz frequency band is able to drive very high data rate up to 480Mb/s with very low power over short distances [1]. CMOS technology is a good candidate for UWB system due to the advantages of low price, small size, high integration, and low power consumption [2]. Therefore, the single chip UWB solutions will appear in the near future can be expected.

The design of power amplifier (PA) for a CMOS UWB transmitter is one of the toughest challenges, because the PA must provide broadband matching, good linearity, low power consumption and reasonable high flat gain over a large frequency spectrum. The UWB PAs for the frequency band of 3.0-5.0 GHz and 3.1-10.6 GHz have been widely implemented in the CMOS technology [3]-[10]. These fabricated UWB PAs reported that the lower power consumptions were 20 mA and all the chips size are about 1 mm². To alleviate the consumed power and the cost on the transmitter design, the power consumption and the chip size should be reduce in designing UWB PA. Another UWB PA was reported for the frequency

band of 6-10 GHz with an inter-stage wideband impedance transformer [13]. This proposed PA has achieved good input matching with lower power gain.

In this paper, the design of CMOS PA from 6.0 to 10.6 GHz for upper band UWB transmitters is presented. Since the output power level of UWB signals must be too low in order to match the power mask of FCC [1], the proposed design only focused on bandwidth, linearity, power consumption and chip size of the UWB PA. A CG topology is employed to achieve wideband input matching. The current-reused technique is used to save power consumption and help to enhance gain at the upper end of the desired frequency. The shunt peaking inductors were used to improve flatness gain and to increase the total bandwidth of the circuit.

II. PROPOSED CG PA There are many topologies have been implemented to

realize wideband PA. Distributed amplifier [3], RLC matching topology [4], and resistive shunt feedback [5] have been reported for broadband PA. Distributed amplifier can provide good matching and linearity over a wideband of frequencies; however, the power consumption and the chip area can be quite high in these circuits. RLC matching also can provide wideband matching and consume less power consumption, but it often needs a number of reactive elements to form the wideband bandpass filter, therefore, occupy large area of a chip and complicated in the layout design as well.

Most reported UWB PA are implemented as a common source (CS) or cascode topology, each of which provides acceptable gain and input matching while dissipating rather low power. However, the CS need good input matching that can be utilize by implemented LC input network or band pass filter at the input, which lead to more than two inductors [3]-[8]. In contrast, a CG topology adopts only one inductor at the input. Moreover, this topology also easily obtained the input matching by setting 1/gm to 50 Ω, where gm is the transconductance of the input transistor [10]. Therefore, the CG topology shows better wideband input matching compare to CS amplifier. In additional, the CG topology has inherent good input output isolation property and better electrostatic discharge (ESD) protection [11].

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The proposed design of UWB CG PA circuit is shown in Fig. 1. It consists of CG input stage, current-reused configuration, second stage common source (CS) amplifier and output buffer. The CG input stage of M1 is employed to achieve the wideband input matching while the spiral inductor Ls is chosen to cancel the imaginary part to produce 50 ohm input impedance.

Figure 1. Complete schematic of the proposed CG PA.

The current-reused topology with the CS transistor of M2 is stacked on top of the input transistor of M1 to save the power consumption [11]. The impedance of L1 is adequately large to provide a high impedance path to block the signal at the desired bandwidth, while the L2 and C2 provide a low impedance path. Therefore, the input signal can be amplifier twice under this technique. A narrow band characteristic composed by the resonate circuit of L2 and C2 is employed to enhance the gain at the upper end of the desired band. The bypass capacitor is required for this topology to provide an ac ground at the source of transistor M2. The choice of large capacitance value of C3 is preferred to provide ideal ac ground. Therefore, the value of C3 is selected to be 20pF. In order to achieve the low power consumption, the width of M1 is set to 75µm while the width of M2 is 45µm. The inductance of L1 and L2 are 5.9 nH and 1.8 nH, respectively. Resistor R1 is used to provide bias voltage for the transistor M2. The inductor L3 is chosen to provide inductive peaking for extending frequency range and provide peak gain at the center of the pass band leading to nearly flat overall wideband PA gain.

The second stage is CS amplifier to increases the gain from the first stage and provides necessary output power demand in UWB transmitters. The biasing voltage for M3 can be applied through R3. The inductor L4 is used to provide shunt peaking effect for the gain flatness and further extend the frequency bandwidth. The last stage consists of transistor M4 and capacitor C5 is the 50 ohm buffer for measurement purpose. The capacitor C1 and C4 is a DC block.

III. SIMULATION RESULTS The circuit design of UWB PA is simulated using Cadence

SpectraRF simulator in TSMC 0.18-µm CMOS process. Fig. 2

shows the post-layout simulation for small signal gain, input and output return loss using S-parameter analysis. The average gain is obtained about 11 dB ± 1 from 6.0 GHz to 10.6 GHz. The maximum gain is 12 dB is achieved at 7 GHz. The input return loss, S11 is less than -8 dB and the output return loss, S22 is less than -11 dB is achieved over the frequency ranges of interest. The other S-parameter including insertion loss, S12 is obtained less than -48 dB as shown in Fig. 3 across the whole band.

The gain is a major performance merit for a power amplifier; however, the linearity is also important. The linearity limits the actual power that can be driven to the load by the PA [5]. The PA can drive the wanted signal without too many harmonic terms only in linear region operation. Two typical linearity merits are output 1-dB compression point (P1dB) and third order intercept point IIP3 (OIP3), which represented the nonlinear gain compression and intermodulation effects respectively [5]. The linearity of the PA is simulated using a periodic steady state (PSS). The input and output 1-dB compression point is -11 dBm and 0 dBm, respectively for the whole band as shown in Fig. 4.

Phase dispersion is also an important specification for wideband communications [8]. The group delay can be used to indicate the dispersion of transmission phase within signal bandwidth. By definition, group delay is the derivation of the phase of S21 where any resonance in the signal path (or pole in S21) will contribute distortion to the group delay [12]. Thus, as shown in Fig. 5, the group delay variation is only ±55.6 ps within the frequency ranges of interest are obtained by the proposed CG UWB PA.

Finally, Fig. 6 shows the stability factor (K-factor) for the proposed CG UWB PA. The PA is unconditionally stable because the K-factor more than one is obtained for the whole frequencies. The layout of the proposed UWB PA is presented in Fig. 7. The die area including the pads is 0.94 mm × 0.82 mm; this layout already sent for fabrication. Table 1 shows the summary of performances and comparison the previously reported UWB PA and this work.

Figure 2. Simulated small signal gain, input and output return loss (post-

layout).

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Figure 3. Simulated insertion loss S12 (post-layout).

Figure 4. Simulated 1-dB compression point (post-layout).

Figure 5. Simulated group delay vs. frequency (post-layout).

Figure 6. Simulated K-factor for stability of CG UWB PA (post-layout).

IV. CONCLUSION In this paper, a 6-10.6 GHz CMOS PA for UWB

applications using CG input stage with current-reused is presented. The proposed UWB PA is aiming for upper band UWB transmitter has been implemented in TSMC 0.18-µm CMOS process. The CG input stage topology shows better wideband input matching and current-reused technique is clearly helped to increase the gain and shunt peaking improve the flatness of the gain at the desired band. The cascade with an additional CS stage topology is used to increase high gain and provides necessary output power demand in UWB transmitters. The post-layout simulation shows that the proposed design has obtained ±1 dB gain flatness with the smallest chip size among the published work. Moreover, good phase linearity is achieved for the whole frequency ranges of interest.

ACKNOWLEDGMENT This work was partly supported by a grant of Knowledge

Cluster Initiative implemented by Ministry of Education, Culture, Sports, Science and Technology (MEXT) and KAKENHI. This work was also partly supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with CADENCE Corporation and Agilent Corporation. The authors also wish to express their appreciation to the support and contributions from those who assist in this research especially Universiti Malaysia Perlis (UniMAP) for providing the short term research grant (9009-00002) that enabled the production of this article.

189.45±55.6 ps

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TABLE I. SUMMARY AND COMPARISON OF UWB PA PERFORMANCES

Reference [13] [14] [15] [16] This work

Technology (µm)

0.18 0.18 0.18 0.18 0.18

Frequency (GHz)

6.0-10.0 3.1-4.8 2.6-5.4 3.0-7.0 6.0-10.6

Supply voltage (V)

1.5 1.0 1.8 1.8 1.5

S11(dB) <-7 <-5 <-5 <-6 <-8

S22 (dB) <-3 <-5 <-6 <-7 <-11

Average Gain (dB)

8.5 18.4 15.8 14.5 11

IP1dB (dBm) N/A -10.6 -3.4 N/A -11

OP1dB (dBm) 5 6 11.4 7 0

GD (ps) N/A N/A N/A ±178.5 ±55.6

Power (mW) 18 22 25 24 18

Chip size (mm²)

1.08 0.97 1.65 0.88 0.77

Input stage topology

CG CS CS CS CG

Figure 7. Layout of the proposed 6.0-10.6 GHz CMOS CG UWB PA on 0.18-µm CMOS technology (0.94mm x 0.82mm).

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