Signaling Scheme for High Speed Die-to-Die Interconnection in Multi-Chip Package (MCP) Technology

Khang Choong Yong1,2, Bok Eng Cheah1, Wil Choon Song1, Mohd Fadzil Ain2

1Intel Microelectronics (M) Sdn. Bhd, Halaman Kg. Jawa, Penang, Malaysia 2School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Penang, Malaysia

Email: khang.choong.yong@intel.com; bok.eng.cheah@intel.com Abstract

Multi-chip package (MCP) technology has recently advanced as an alternative packaging solution to enable high performance and power-efficient mobile electronic devices. The wide adoptions of MCP technology are mainly driven by reduced circuit complexity, heterogeneous integration across different silicon process technology and shorter product cycle time. However, the high density on-package die-to-die (D2D) interconnects within package presents unique signaling challenges as the operating frequency continue to rise. This paper analyzes various low power passive signaling enhancement techniques e.g. equalization and termination to mitigate the signal integrity challenges of the high speed on-package D2D channels. The effectiveness of various signaling enhancement techniques and topologies were studied and compared in terms of eye opening and overshoot performances. The combination of series-source termination and parallel-load termination was found to be a feasible candidate in view of optimum trade-off between performance and silicon real-estate or costs. Simulation results show the recommended topology is able to achieve 300mV/40ps eye opening at 15Gbps.

1. Introduction The MCP technology that integrates two or more silicon

dies on a package substrate has recently emerged as another compelling solution to enable high performance and power efficient electronic devices e.g. tablets, smart-phones and small form-factor laptops. The wide adoptions of MCP technology are mainly driven by reduced circuit complexity and lower input/output (I/O) drive strength that are essential in trimming down the overall device power consumptions. In addition, the MCP technology offers heterogeneous integration across various silicon process technology nodes and manufacturers to enable mixed signal applications with shorter product cycle time [1].

The on-package D2D interconnects that electrically couple the silicon dies in the MCP are typically single-ended bus in order to achieve higher bandwidth and maximum data rate per unit area [2]. High density routing is unavoidable for such interconnection due to the confined package gap (typically in the range of millimeters) between the silicon dies [Figure 1]. The combination of high density routing and increased operating frequency presents unique electrical challenges e.g. signal quality degradations due to signal reflections and crosstalk coupling effects [3].

This paper focuses on the evaluation of various low power passive signaling enhancement techniques such as equalization and termination to mitigate the signal integrity challenges for the on-package D2D interconnects [4]. The

effectiveness of various signaling enhancement techniques and topologies were compared from the perspective of voltage and timing performances. Quality and reliability parameter such as signal overshoot at the receiver device was also covered in this study. The optimization of signaling enhancement strategy to enable high speed MCP is further elaborated in this paper.

Figure 1: Multiple-chip package with D2D interconnects (a) top view and (b) cross-section view.

2. Simulation and Assessment Methodology In this assessment, the simulation topology comprised a

transmitter, package bump break-out, stripline main route, package bump break-in and the receiver as illustrated in Figure 2. Linear buffer models were employed at both driver and receiver in this point-to-point on-package D2D routing topology. The driver was modeled as voltage source with a serial resistance (RDRV) of 5-65 and shunt capacitance (CDRV) of 0.35pF; meanwhile the receiver was modeled as an input capacitance (CRCV) of 0.5pF [5]. The transmission line models for both break-out and break-in were extracted using Ansoft® HFSS™, and the main route was modeled using experimental validated 2D simulator tool based on actual package design layout. The crosstalk effect can be considered negligible beyond second order of the adjacent aggressors in an equally spaced single ended channel. Thus, a total of 5 transmission channels, with the victim channel routed in between 2 sets of aggressors at each side, were established to envelop the crosstalk impact in this study [2].

Figure 2: On-package D2D interconnects topology.

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In this study, the examined transmission channel was assumed as a linear-time-invariant (LTI) system. The worst case bit pattern generated by peak distortion analysis (PDA) tool was applied to evaluate the worst case eye opening. The full channel simulation was carried out using HSPICE 2009. The frequency was swept from 2.5GHz up-to 7.5GHz, with step size of 2.5GHz. The on-package interconnects channel length was evaluated from the range of 3mm up-to 15mm. The nominal voltage supply was fixed at 1.1V. Key silicon parameter sweep, such as RDRV (50 to 60 ) and slew rate (20%-40%UI), were also covered in this analysis.

Multiple combinations of low-power passive signaling enhancement techniques e.g. equalization and termination were assessed in order to identify the optimum solution(s) for high speed on-package interconnects. Figure 3 illustrates the signaling enhancement schemes applied in this analysis. The termination (i.e. series and parallel) and equalization (i.e. low-pass and high pass filters) schemes were evaluated at both driver and receiver. The attributes of the respective enhancement techniques are further summarized in Table 1. Meanwhile, the practical ranges of each parameter sweeps are further depicted in Table 2. The impacts and signal quality improvement trends of the respective schemes were analyzed and pitted against the baseline reference (Figure 2) in terms of eye opening and signal overshoot.

Figure 3: Low-power signaling enhancement schemes.

Type Termination Equalization

Series Parallel Low Pass High Pass

A

B

C

D

E

F

G

H

Table 1: Termination and equalization schemes

Parameter Sweep Range

RDRV 5 -65

CDRV 0.5pF

L 0.5nH-5nH

C 0.4pF-15pF

RSeries 10 -30

RParallel 30 -160

CRCV 0.35pF

Table 2: Parameter-sweep range

3. Simulation Results and Discussions In this section, the electrical performance of the high

speed on-package D2D interconnects design with signaling enhancement schemes are analyzed and compared against the baseline reference as shown in Figure 2. Figure 4 shows the comparisons of signal quality of the evaluated topologies in terms of eye opening and signal overshoot. The signaling schemes were mainly grouped into two categories i.e. the termination scheme (A,D,E,F) represented by the blue-curve and the equalization scheme (B,C,G,H) represented by the red-curve. Meanwhile, the dotted black-curve represents the reference benchmark.

Figure 4: Signal quality trends of the assessed topologies across frequency and channel length.

In general, the equalization and termination schemes

applied in this assessment yield better signal integrity performance compared to the baseline reference in terms of eye opening and signal overshoot at the receiver device. The termination scheme was found more effective compared to the equalization approach in signal quality enhancement for on-package D2D MCP channel. Pre-eminent eye opening and overshoot were consistently sighted across the operating

174 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)

frequency and channel length with the termination approach. Meanwhile, consistent improvements on signal overshoot and eye height margin over the reference benchmark were also sighted with the equalization scheme. However, the equalization scheme did not show apparent improvements in term of eye width margin compared to reference benchmark. This observation is mainly due to the dominant factor of crosstalk coupling that deteriorates the signal traverse across the on-package D2D channel [3].

Although the source termination alone (represented by the reference benchmark) is able to minimize the multiple reflections that lead to the inter-symbolic interference (ISI), it was found insufficient to address the crosstalk effect due to the highly coupled on-package D2D interconnects. Severe signal quality degradation on the tightly coupled on-package D2D interconnects was found contributed by the near-end crosstalk (NEXT) noise that resulted from the signal reflections at the receiving end of aggressor(s). Therefore, addressing the signal distortion was found more critical compared to the rise and fall time degradations that due to channel dielectric and conductor loss in the tightly coupled on-package D2D channels. In addition, the high-frequency losses such as skin effect and dielectric loss are typically insignificant for short channel length [6]. Receiver device load termination was found to be an essential element to mitigate the signal distortion resulted by the NEXT in addition to address the conventional ISI phenomenon due to signal reflections.

Figure 5: Signal integrity plot of termination schemes at the driver and/or receiver device.

In this section, several termination configurations were

established to further investigate the efficacy of termination scheme for high speed MCP applications. Figure 5 shows the simulation results of termination strategy employed at the respective driver and/or receiver devices. Termination at driver represents type (A) signaling enhancement scheme in Figure 3. In the meantime, type (D), (E) and (F) signaling enhancement schemes were represented by the termination at receiver. Combinations of termination at both driver and

receiver device were also enveloped in the analysis. It was found that the termination option at both driver and receiver devices provide considerable signaling quality improvement over termination at the driver or termination at the receiver. Significant improvements of the eye height opening and overshoot were observed as the frequency increases. This observation is mainly contributed by the effectiveness of termination configuration at both driver and receiver to mitigate the signal reflections at the driver and the induced NEXT at the receiver due to impedance mismatch.

Subsequently, the receiver termination schemes were further breakdown into 3 categories as illustrated in Figure 3 i.e. series termination (D), parallel termination (E) and the combined series and parallel termination (F) to identify the optimum design settings. The signaling performance of the respective receiver termination approaches are presented in Figure 6. Noticeably, the combined series and parallel termination (green-curve) yielded the most prominent signaling performance compared to the parallel termination (purple-curve) and the series termination (brown-curve) options. This phenomenon is primarily contributed by the capability of the combined series and parallel termination (F) to provide both high and low frequency component matching. The series termination is able to provide only the high frequency component matching meanwhile the parallel termination is only capable to yield the low frequency component matching. At higher data rate, larger mismatch of high frequency component is sighted at the receiver input capacitance due to increased signal bandwidth. Therefore, obvious voltage margin delta was observed as the frequency surges.

Figure 6: Signal integrity plot of various receiver termination schemes.

However, it is observed the signaling performance delta between the combined series and parallel termination (F) and the parallel termination (E) is insignificant. Therefore, it is ascertained through this study that the combination of series source termination (A) and parallel load termination (E) (as illustrated in Figure 7) is a viable candidate for high speed MCP applications when silicon real-estate and costs

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are being considered. Figure 8 depicts the eye diagrams of various signaling enhancement schemes compared to the reference baseline (Figure 2) operating at 7.5GHz and 15mm on-package D2D channel length. The simulation parameters are summarized in Table 3.

Figure 7: Recommended signaling enhancement scheme for high speed MCP applications.

(a) Reference Baseline

(b) Parallel-Load Termination

(c) Series-Source Termination

(d) Series-Source + Parallel-Load Termination

Figure 8: Eye diagrams of various signaling enhancement schemes compared to the reference baseline at 7.5GHz on

15mm channel length.

Table 3: Simulation parameters

Simulation results show the recommended signaling enhancement scheme i.e. implementation of series source termination and parallel load termination in MCP topology is able to significantly improve the signaling performance. Meanwhile, the collapsed eye sighted on the reference baseline also further reinforces the necessity of signaling enhancement schemes to enable the high speed on-package D2D interconnects for MCP applications. The implemented source-series termination (R1) helps to mitigate the overall bandwidth limitations at the driver. In addition, the source-series termination (R1) also provides an alternative to achieve reduced driver impedance in order to minimize the RC-limit without trading off the impedance matching along the channel. With the assumption of the discrete package resistor has negligible parasitic capacitance, the overall system bandwidth limitation and the channel impedance mismatch are addressed [7]. Hence, higher operating data rate and longer on-package D2D channel can be enabled for MCP applications.

Conclusions In short, this study has successfully evaluated various

low power passive signaling enhancement techniques to enable high speed multiple-chip package applications. The termination scheme was found more effective in improving the overall signaling performance compared to equalization approach. This observation is mainly due to the dominating crosstalk factor yielded from the tightly coupled on-package D2D interconnects. Meanwhile, substantial improvement on the eye opening and signal overshoot were recorded with termination at both the driver and receiver devices compared to single termination at the driver or receiver alone. This observation highlights the effects of signal reflections (at the driver) and the induced NEXT (at the receiver) due to impedance mismatch need to be carefully addressed. The combined series and parallel load termination was found effective in providing prominent signaling performance due to the capability to achieve both low and high frequency component matching. Nevertheless, the configuration of series-source termination and parallel-load termination was found a viable candidate when silicon real-estate and costs are being considered. Preliminary simulation results show the recommended topology is able to achieve 300mV/40ps eye opening (diamond mask) at 15Gbps and 15mm channel length.

Acknowledgments The authors would like to convey their gratitude to Intel

Architecture Group-Malaysia management for the support of this research. The invaluable technical discussions with fellow members from Mobile and Communications Group (MCG) and IDGz HardIP are also gratefully acknowledged.

References [1] Ang, B.C., “Multi-Chip Packaging (MCP) or Not

MCP?,” Proc International MultiConference of Engineers and Computer Scientists (IMECS), Hong Kong, Mar. 2012, pp. 1236-1239.

176 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)

[2] Vega-Gonzalez, V.H.; Torres-Torres, R.; Sanchez, A.S., "Analysis of the Electrical Performance of Multi-Coupled High-Speed Interconnects for SoP," Proc 52nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Cancun, Aug. 2009, pp.1030-1033.

[3] Yong, K.C.; Song, W.C.; Cheah, B.E.; Ain, M.F., “Signaling Analysis of Inter-Chip I/O Package Routing for Multi-Chip Package,” Proc 4th Asia Symposium on Quality Electronic Design (ASQED), Penang, Jul. 2012, pp. 271-276.

[4] Zhang, L.; Yu, W.; Zhang, Y.; Wang, R.; Deutsch, A.; Katopis, G.A.; Dreps, D.M.; Buckwalter, J.; Kuh, E.; Cheng, C., “Low Power Passive Equalizer Design for Computer Memory Links,” Proc 16th IEEE Symposium on High Performance Interconnects, Stanford, CA, Aug. 2008, pp. 51-56.

[5] Guo, W.-D.; Tsai, F.-N.; Shiue, G.-H.; Wu, R.-B, “Reflection Enhanced Compensation of Lossy Traces for Best Eye-Diagram Improvement Using High-Impedance Mismatch,” IEEE Transactions on Advanced Packaging, Vol. 31, No.3 (2008), pp. 619-626.

[6] Han, K. J.; Takeuchi, H.; Swaminathan, M., "Eye-Pattern Design for High-Speed Differential Links Using Extended Passive Equalization," IEEE Transactions on Advanced Packaging, Vol. 31, No.2 (2008), pp. 246-257.

[7] Hall, S. H. et al, High Speed Digital System Design - A Handbook of Interconnect Theory and Design Practices, John-Wiley & Sons (New York, 2000).

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