ICSE 2008 Proc. 2008, Johor Bahru, Malaysia

Pre-silicon MOSFET Mismatch Modeling for Early Circuit Simulations

Muhamad Amri Ismail1,2, Iskhandar Md Nasir1 and Razali Ismail2

1MIMOS Semiconductor, MIMOS Berhad,

Technology Park Malaysia, 57000 Kuala Lumpur, MALAYSIA Email: amris@mimos.my, iskhand@mimos.my

2Department of Microelectronics and Computer Engineering, Universiti Teknologi Malaysia, 81300 Skudai, Johor, MALAYSIA

Email: razali@fke.utm.my Abstract - The continuing scaling down of CMOS technologies contributes to the important of having early circuit simulations even before any real silicon data are available. This paper presents a methodology to extract a pre-silicon MOSFET mismatch model using backward propagation of variance (BPV) technique. All the required steps such as the correlation of process and electrical parameters through BSIM3v3 SPICE model and explanation of mathematical relationships among the parameters are discussed. The experimental data for mismatch analysis are projected from 0.35 um process to 0.25 um and 0.18 um processes using the technology scaling coefficient coupled with the related statistical data analysis. The good agreement between experimental and Monte Carlo SPICE simulation data verifies the proposed extraction methodology.

I. INTRODUCTION MODELING of MOSFET mismatch is vital in representing within-die process variations because it related to the design yield. Circuit designs such as band-gap voltage reference and current mirror in analog as well as 6T-SRAM design in digital application would need an accurate mismatch model to predict these small variations [1]. The modeling exercise typically required a huge number of measurement data and it is a time consuming process. The process from mask development until the wafer fabrication would need designers to wait for a long process qualification steps before the stable measurement data are available for further statistical data analysis. Therefore it is necessary

to have an early circuit design while waiting for the qualified process to reduce the design cycle. Pre-silicon models are required for the purpose of early statistical circuit simulations. The type of mismatch models for circuit simulation varies from a simple model such as Level 3 to complex model such as BSIM3v3 [2]. Recently Drennan et al have reported the mismatch analysis with respect to the physical process parameters using BPV technique [3]. Various literatures have been published in relating the pre-silicon data with the actual device parameters and inter-die process variations. None of the previous reports has made an attempt to project the MOSFET mismatch model from one technology to another. This paper presents a systematic methodology in deriving pre-silicon mismatch model suitable for early circuit simulations. Section II details the generation of pre-silicon data and extraction of process mismatch coefficient with BPV technique follows with experiment part in Section III. Section IV is result and discussion while conclusion is in Section V.

II. PROJECTION OF MISMATCH MODELS There are two methods reported in the literatures for the accurate pre-silicon data namely TCAD optimization and device model optimization techniques. The first technique, based on TCAD tool contains some limitations such as the provided models for many processes are still in development stage, process-equipment variability and no narrow width effects from simple 2-D simulation [4]. The latter technique is based on the advanced physical MOSFET model to project the device parameters from current

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ICSE 2008 Proc. 2008, Johor Bahru, Malaysia

available technology to future technology development [5]. This technique could provide a very accurate projected device characteristic with easier implementation thus suitable to reduce the technology development cycle. For that reason, BSIM3v3 model is used in this work to produce the related predictive model. The main objective of this work is to come out with a complete set of MOSFET mismatch model parameters for different CMOS technologies. There are two main stages involve during the projection exercise where stage 1 represents the current technology and stage 2 represents the projected technologies. Current technology in this work is 0.35 um while the projected technologies are 0.25 and 0.18 um. Figure 1 shows the simplified flow diagram of the first stage. The purpose of this initial stage is to extract MOSFET mismatch model parameters and related process mismatch coefficients from the actual silicon wafer. The flow starts with the requirement of having a few good wafers for the measurement. Normally these wafers passed the standard PCM test with more than 90% yield and have a special test structures fabricated together for purpose of testing. Typical BSIM3v3 model parameters are extracted from the measured IV and CV curves while the mean ( ) and standard deviation ( ) values are derived from the mismatch measurement data. These measured and values are the golden target in the next mismatch model extraction step. Pelgrom’s model is used as a reference in determination of mismatch model parameters where MOSFET mismatch is a function of gate area [6]. As an example the mismatch model for threshold voltage is given by ( )

LW

AV TV

T ⋅=∆σ (1)

where VT is the Vth difference between the two identical transistors and AVT is the mismatch model coefficient. Typical threshold voltage (vth0) and mobility (u0) parameters are used to represent threshold voltage and drain current mismatch. Physical phenomenon parameters such as DIBL effect and sub-threshold swing factor parameters could also be used to improve the mismatch prediction in sub-threshold regime. The extracted mismatch model parameters are verified by a good agreement between mismatch measurement data and Monte Carlo statistical simulation results.

Fig. 1 Flow diagram for generation of MOSFET

mismatch model from measured 0.35 um process in stage 1

The next step after mismatch model extraction is the derivation of the related process mismatch coefficient. BPV technique is used where the variances of electrical parameter e and sensitivity analysis from SPICE simulation are required to derive the variance of process parameter p, given by the following mathematical relationship:

E = S . P (2) where E is the vector of variance e, S is the matrix of sensitivity analysis and P is the vector of variance p. The vector of E is known where they are actually the variance ( 2) values from the drain current mismatch measurement. The matrix of S is also known where it contains the squares of sensitivity analysis obtained from SPICE simulation. The vector of P is the only unknown data which is needed to be solve numerically using any non-linear regression technique. Typical BSIM3v3 model is required in computing the matrix of sensitivity analysis S as well as correlation of critical process and electrical parameters as shown in Table 1. These parameters will be used in evaluating the drain current mismatch with respect to small changes of BSIM3v3 process parameters.

Good wafers

BSIM3v3 model

extraction

Mismatch measurement

data ( �� )

Mismatch model

extraction (vth0, u0)

Monte Carlo simulation

Model verification

BPV technique

Process mismatch coefficient (tox, lint,

wint, etc)

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ICSE 2008 Proc. 2008, Johor Bahru, Malaysia

Table 1. Process and electrical parameters in BSIM3v3 model used in BPV technique BSIM3v3 parameters

Description Unit

TOX Gate oxide thickness m LINT Length offset fitting parameter m WINT Width offset fitting parameter m NCH Channel doping concentration 1/cm3 XJ Junction depth m Output from the first stage such as typical BSIM3 model and process mismatch coefficients which become the main input for the second stage as shown in Figure 2. The purpose of the second stage is to release the pre-silicon mismatch models for future technology development such as 0.25 and 0.18 um CMOS. It is understood that there is still no available silicon data for the projected technology in the early stage. Therefore the predictive device model is generated from the typical BSIM3v3 model considering the approach published by Orshansky et al [5]. Fig. 2 Flow diagram for generation of pre-silicon

MOSFET mismatch model in stage 2

The model parameters such as Tox, Lint, Vsat, Rdsw and Xj are specified physically to meet the new projected technology while Vth0, Nch and U0 are adjusted to meet the targeted new electrical specifications. In modeling the mismatch effect, the related mismatch values of electrical parameters are critical as an experimental data. Although the actual wafers are not yet available, these data could be generated by applying the well conditioned BPV technique to the projected BSIM3v3 model. Considering (2), at least two variables need to be identified while the last variable could be solved numerically with non-linear regression fitting. In the second stage E is basically the unknown while S and P need to be identified. S is generated by applying the sensitivity analysis of various drain current with respect to selected process parameters as shown in Table 1. P is generated by applying the constant field scaling coefficient to the original process mismatch coefficient of 0.35 um. The VFDOLQJ�FRHIILFLHQW� �LV�JLYHQ�E\ ���� %DVH�WHFKQRORJ\��3URMHFWHG�WHFKQRORJ\������� Then (2) is solved and E would represent the mismatch experimental data for the projected technology. Predictive BSIM3v3 model is enhanced to make it suitable for Monte Carlo statistical simulations. The pre-silicon mismatch model is released once the simulation and experiment data are in a good agreement, usually with the RMS error less than 10%.

III. EXPERIMENT In deriving the pre-silicon mismatch model we have measured and simulated various drain current characteristics. Drain current mismatch data required in developing BPV technique to show the relationship between process and electrical parameter variations. The details of measurement conditions are shown in Table 2. Linear region is when Vds=0.1 and saturation region is when Vds=Vdd. Different value of Vg represent the inversion characteristics namely weak, moderate and strong while both Vs and Vb are equal to 0. For 0.35 um process, the measurements are performed on the actual wafer and the sensitivity analyses are simulated using extracted BSIM3v3 to find the actual mismatch process coefficients. For 0.25 and 0.18 um technologies, the sensitivity analysis are simulated using projected

Yes

Predictive BSIM3v3

model

Scaled process

mismatch coefficient

Mismatch experimental

data ( 2)

Model released

Good agreement

No

Pre-silicon mismatch

model (vth, uo)

Process mismatch coefficient

Typical BSIM3v3

model

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ICSE 2008 Proc. 2008, Johor Bahru, Malaysia

BSIM3v3 to find the experimental data of electrical parameter variances from the scaled mismatch process coefficients. Table 3 shows the details of related BSIM3v3 model parameters in developing the predictive model. Table 2. Measurement conditions for drain current mismatch Region Vg=0 Vg=Vdd/4 Vg=Vdd/2 Vg=Vdd Linear Ioff_lin Idlin_weak Idlin_mod Idlin_str Saturation Ioff_sat Idsat_weak Idsat_mod Idsat_str Table 3. Summary of projected BSIM3v3 model parameters

CMOS technologies (um) Parameters 0.35 0.25 0.18

Leff (um) 0.2 0.12 0.09 Tox (nm) 7.5 5 4 Vdd (V) 3.3 2.5 1.8 Vth0 (V) 0.4 0.35 0.27 Rdsw (��XP� 900 700 250 Nch (cm-3) 0.18E18 0.35E18 0.60E18 Vsat (m/sec) 80E3 100E3 140E3 The measured and simulated data for each technology are collected from different combinations of channel length and width where five structures which cover the different size of area are used.

IV. RESULT AND DISCUSSION Table 4 shows the actual mismatch process coefficients for 0.35 um as well as projected coefficient for 0.25 and 0.18 um. Levenberg-Marquardt non-linear least square algorithm developed with MATLAB tool is used to solve (2) for the mismatch process coefficient. Table 4. Mismatch process coefficients for difference CMOS technologies

CMOS technologies (um) Parameters 0.35 0.25 0.18

Tox [um] 0.7804 0.5574 0.4107 � [um3/2] 4.8099 3.4356 2.5315

� [um3/2] 8.0234 5.7310 4.2228 Nch [um] 10.2758 14.3861 19.5240 Xj [um] 0 0 0

The data shows that the channel doping concentration is the most sensitive process parameter which contributes to the MOSFET mismatch for the particular process. The

effective channel length and width parameters also produce some influences to the mismatch analysis but the effect reduced for smaller technology nodes. Pelgrom’s plots are generated to show the different between measured and simulated data. The simulated data are obtained by performing a Monte Carlo statistical simulation. Figure 3 and 4 present the result for 0.35 um technology. Instead of various drain current measurements, threshold voltage measurements are also done to extract the related threshold voltage mismatch coefficient. The small error between measured and simulated data verified that the extracted mismatch model is accurate.

NMOS Idsat mismatch for 0.35 um

0

0.4

0.8

1.2

1.6

2

0 0.2 0.4 0.6 0.8 1 1.2 1.4

1/sqrt(Area) [1/um]

Std

dev

of d

elta

Idsa

t

[%]

Measured

Simulated

Fig. 3 Idsat mismatch for 0.35 um NMOS device

NMOS Vth mismatch for 0.35 um

0

2

4

6

8

10

12

0 0.2 0.4 0.6 0.8 1 1.2 1.4

1/sqrt(Area) [1/um]

Std

dev

of d

elta

Vth

[

mV

]

Measured

Simulated

Fig. 4 Vth mismatch for 0.35 um NMOS device

Figure 5 and 6 present the result of drain current mismatch at linear and saturation regions for both 0.25 and 0.18 um processes. The experimental data are obtained from the BPV technique and it shows a good agreement with the pre-silicon mismatch model. The model is very accurate for the device with large area and there are only slight discrepancies for the device with smaller area which is understandably due to mismatch theory and difficulties of predicting the narrow width effects. These plots proved that the provided mismatch model is suitable for the early circuit design.

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ICSE 2008 Proc. 2008, Johor Bahru, Malaysia

NMOS Idsat mismatch for 0.25 and 0.18 um

0

0.4

0.8

1.2

1.6

2

2.4

0 0.5 1 1.5 2 2.5 3 3.5

1/sqrt(Area) [1/um]

Std

dev

of d

elta

Idsa

t

[%]

Exp_025

Sim_025

Exp_018

Sim_018

Fig. 5 Idsat mismatch for pre-silicon data

NMOS Idlin mismatch for 0.25 and 0.18 um

0

0.4

0.8

1.2

1.6

2

2.4

0 0.5 1 1.5 2 2.5 3 3.5

1/sqrt(Area) [1/um]

Std

dev

of d

elta

Idlin

[

%]

Exp_025

Sim_025

Exp_018

Sim_018

Fig. 6 Idlin mismatch for pre-silicon data

Although the pre-silicon mismatch model is developed using BPV technique which only considered drain current parameters as the input, the threshold voltage coefficient could be extracted by performing further Monte Carlo simulation for threshold voltage as shown in Figure 7.

NMOS Vth mismatch for 0.25 and 0.18 um

0

4

8

12

16

20

0 0.5 1 1.5 2 2.5 3 3.5

1/sqrt(Area) [1/um]

Std

dev

of d

elta

Vth

[

mV

]

Sim_025

Sim_018

Fig. 4 Vth mismatch for pre-silicon data

The electrical mismatch coefficients for threshold voltage (AVth) and drain current (AId) are extracted from the slope of the Pelgrom’s plots and the results shown in Table 5. The data shows that the provided pre-silicon mismatch models are actually follow the general trend in

mismatch analysis as published by Kinget and Maxim et al [1],[2].

Table 5. Mismatch coefficient for Vth and Id

Technology AVth (mV.um) AId (%.um) 0.35 um 9 1 0.25 um 7 0.75 0.18 um 5 0.5

V. CONCLUSION

In this paper, we have presented a systematic methodology to extract pre-silicon MOSFET mismatch model suitable for early circuit simulations. This work took the advantages of accurate pre-silicon device model generation and well conditioned technique of BPV. The experimental data are obtained from the projected mismatch process coefficients with related HSPICE sensitivity analysis on the various drain current data through BPV technique. The small error between experimental and Monte Carlo simulation data proved that we have successfully project the mismatch model from 0.35 um process to 0.25 and 0.18 processes.

REFERENCES [1] P.R. Kinget, “Device Mismatch and Tradeoffs

in The Design of Analog Circuits,” IEEE Journal of Solid-State Circuits, vol. 40, no. 6, pp. 1212-1224 (2005).

[2] A. Maxim and M. Gheorge, “A Novel Physical Based Model of Deep-Submicron CMOS Transistor Mismatch for Monte Carlo SPICE simulation,” Proc. of International Conference on Circuits and Systems, pp. 511-514 (2001)

[3] P. G. Drennan and C. C. McAndrew, “Understanding MOSFET Mismatch for Analog Design,” IEEE Journal of Solid-State Circuits, vol. 38, no. 3, pp. 450-456 (2003).

[4] H. Sato, H. Kunitomo, K. Tsuneno, K. Mori and H. Masuda, “Accurate Statistical Process Variation Analysis for 0.25-um CMOS with Advanced TCAD Methodology,” IEEE Trans. Semiconduct. Manufact. vol. 11, no. 4, pp. 575-582 (1998).

[5] M. Orshansky, J. An, C. Jiang, B. Liu, C. Riccobene and C. Hu, “Efficient Generation of Pre-Silicon MOS Model parameters for Early Circuit Design,” IEEE Journal of Solid-State Circuits, vol. 36, no. 1, pp. 1212-1224 (2001).

[6] M. J. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, “Matching Properties of MOS Transistors,” IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1433-1440 (1989).

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