Mobility Enhancement on Vertical Strained-SiGe Impact Ionization MOSFET Incorporating Dielectric

Pocket (VESIMOS-DP)

Ismail Saad, Mohd. Zuhir H., Bun Seng C., Abu Bakar AR, N. Bolong, Khairul A.M, Bablu Ghosh.

Nano Engineering & Material (NEMs) Research Group, School of Engineering & IT, Universiti Malaysia Sabah,

88999, Kota Kinabalu, Sabah. ismail_s@ums.edu.my

Razali Ismail Computational Nanoelectronics (CONE) Research Group,

Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Skudai 81310, Malaysia.

zuhirhamzah@yahoo.com

Abstract—The Vertical Strained Silicon Germanium (SiGe)

Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. The electron mobility in the VESIMOS-DP (~1440m2/V-s), was found to be increased by 4% in comparison to VESIMOS (~1386 m2/V-s) device. The mobilities in strained layer is depends on the transport direction, either parallel to the original SiGe growth interface or in the perpendicular direction. Carrier mobilities in strained SiGe layer is also based on the local distortion due to the strain effects which contribute to the alloy scattering on the carriers. With the vicinity of DP, the carrier scattering effect has reduced which merits the introduction of DP on the device. Due to the DP layer, improve stability of threshold voltage, VTH and subthreshold slope, S was found for VESIMOS-DP device of various size ranging from 20nm to 80nm justified the vicinity of the DP on improving the performance of the device.

Keywords—IMOS, Dielectric Pocket, VESIMOS, VESIMOS-DP, Parasitic Bipolar Effects, nano-electronics

I. INTRODUCTION Since the invention of first electronic application,

increasing the speed and improving the package density has been a constant challenge in the microelectronic industry. Electronic devices are so small, that billions of basic functions are accessible in a handheld system. As transistors progress deeper into the nanometer scale, the industry standard has gone from 65 to 45 to 32 and now to 22 nanometers. Device scaling makes this possible. With scaling or miniaturization, silicon device has become smaller, faster and better in performance yet using fewer material than before.

Recently the channel length has approached 100 nm and bulk MOSFET have reached their physical shrinkage limits. Most of the challenges faced when the channel length below 100 nm are related to short channel effects mainly due to drain-induced barrier lowering (DIBL) effect. As CMOS is scaled down, the drain field penetration into the channel becomes more serious. This worsens the DIBL and the threshold voltage roll-off characteristics [1]. To continue the shrinkage path, it has been necessary to propose new materials and new device structures of the MOSFET. In order to face the theoretical limit of 60 mV/dec of sub-threshold slope, S, a device that work on

the principle of impact ionization MOSFETs (IMOS) has been developed successfully [2].

IMOS device works on the principle of avalanche breakdown mechanism by modulating the channel length to switch between OFF states and the ON states. The planar IMOS has low subthreshold slopes which indicate good ION/IOFF ratio and low subthreshold leakage currents [3-6]. However, it requires high supply voltages which results in hot carrier degradation effects. Thus, suffers from poor reliability issues [7-9]. Vertical IMOS is developed and investigated to counter these effects [10-13]. It suppress leakage current at high temp and shows superb subthreshold slope of 4 mV/dec as well as good ION/IOFF current ratio. Most importantly, it showed no hot carrier effects. However, it need high supply voltage, VDS in order to achieve the desired device characteristics and suffers a remarkable hysteresis [14-15].

Strained SiGe has attracted much attention because of the hole mobility enhancement and compatible with current Si technology. Strained SiGe on vertical IMOS has been developed and investigated [16-17]. This compressive strain developed results in high carrier mobility, high impact ionization rates and better ON-OFF current ratios, besides retaining the good subthreshold slopes shown by vertical IMOS devices. However, this device suffers low breakdown voltage and parasitic bipolar transistors (PBT) effect [18-19].

In this paper, the effect of integrated Dielectric Pocket (DP) into Vertical Strained-Sige Impact Ionization MOSFET (VESIMOS) on the performance of the device in terms of mobility, subthreshold swing, threshold voltage and drain current has been observed. It has been predicted that the compressive strain in the SiGe layer splits the light and heavy hole subbands and improves the hole mobility in both out-of-plane and in-plane directions [20-21]. The introduction of DP in the channel region also improves the threshold voltage stability, electron velocity of the device and suppressed the parasitic bipolar transistor effect (PBT). Hence, improve functionality of the device.

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II. DEVICE DESIGN Figure 1 shows the detailed cross-sections of the device

structure which simulated for performance analysis of the Vertical Strained-SiGe Impact Ionization MOSFET with dielectric pocket (VESIMOS-DP) using Sentaurus package [26]. This structure comprises a source and a drain region with n+ doping, an intrinsic channel containing a highly doped δp+ layer (Boron = 4x1019/cm3) and two sided gates. The high doping of the delta layer which creates a large potential barrier, makes it possible to achieve high electric fields in the intrinsic zone near the drain without applying a very high drain–source voltage, VDS. Careful selection of the delta layer thickness is recommended as to have good sub-threshold slopes. Hence, an optimum value of delta layer thickness and doping was chosen to get desired sub-threshold slopes. The intrinsic-Si, i-Si regions reduce the lateral electric field near source and the drain [22]. Therefore, an optimum thickness for i-Si region has been chosen, so that they could effectively reduce the lateral electric fields. Due to the presence of i-Si regions between highly doped S/D regions, the impurity scattering is also reduced. The strained layer thickness was 20nm with Ge=30%. The DP layer thickness was also 20nm. However, the DP layer thickness was varied to examine its effects towards device performance. The DP layer was also sandwiched with intrinsic Silicon caps with 5nm thickness. This Si-cap acts the same function as i-Si to improve the stability of the overall device.

Fig. 1. VESIMOS-DP device structure with respective layer thickness of source, drain, δp+, i- Si, SiGe, Si-cap and DP.

The Ge mole fraction is related to the amount of strain in the SiGe layer. The Ge mole fraction used was 30%, initially. Later, the mole fraction was varied from 10% to a maximum mole fraction of 50%. The lower the mole fraction, the lower is the strain. Hence, by varying the amount of strain, the device performance was analyzed. The Source was n-doped with Antimony with a doping concentration of 2.08x1018 /cm3. The Drain was also n-doped with Phosphorus with a doping concentration of 2.08x1018 /cm3. The high doped S/D doping was chosen as the device concept was based on impact ionization that require high electric field of drift current.

III. RESULT AND DISCUSSION

The transfer characteristic is examined by biasing the drain voltage, VDS and ramping the gate voltage, VGS at defined bias steps. Fig. 2 shows the comparison of transfer characteristic, IDS-VGS of VESIMOS-DP with different DP thickness. Fig. 2 revealed that VESIMOS-DP works well for low VDS which has overcome the problem faced by the conventional IMOS devices [12-15]. The energy of electrons required in the II region is much lower compared to the lateral IMOS since the II is not the only mechanism contributing to the extremely fast rising drain current. Instead, the holes generated by the II accumulate in the δp+ layer region will charged the body of the transistor and causing a dynamic reduction of threshold voltage during the switched ON.

Fig. 2. Transfer Characteristics, IDS-VGS of VESIMOS-DP for Si0.7Ge0.3, S/D doping = 2.0x1018/cm3, NA = 4.0x1019/cm3 VDS=1.75V.

Threshold voltage, VTH was found to be stable across various DP size from 20nm to 80nm. This stable VTH =1.35V obtained due to the vicinity of DP layer near the drain end has reduce charge sharing between the source and drain. The slight different and consistency of VESIMOS-DP subthreshold value (S = 19 mV/dec) has given advantages for incorporating DP layer near the drain end. This subthreshold voltage obtained is much lower than the conventional MOSFET limit which is 60 mV/decade due to the impact ionization mechanism of VESIMOS-DP device.

In addition, the output characteristic was also highlighted a very good drain current at different gate voltage with the increasing of drain voltage as shown in figure 3. It was happen due to the existence of strain SiGe at the channel region has enhanced the carrier transport in the VESIMOS-DP channel. It can be seen from figure 3 that initially the drain current rises sharply and then increases gradually before going into breakdown state. The sharp rise in drain current can be attributed to the presence of Ge. Germanium has high and symmetric impact ionization rates (αN ≈ αP), which ensures that the transition from OFF state to the ON state is abrupt.

Fig. 3. Output characteristics of VESIMOS-DP device at different gate voltage.

For VGS > 1.80V, the device instead of going to the bipolar mode as in VESIMOS without the DP layer, it undergoes breakdown state. In bipolar mode, the n+ source region acts as emitter, the n+ drain acts as collector and δp+ layer as a base as illustrated in the figure 1. The holes generated by impact ionization acts as a base currents and drain source current increases as the current of the parasitic bipolar transistor (PBT) is switched on. This additional current amplification mechanism contributes to the lower subthreshold slope, but with a certain hysteresis [10] due to the PBT effect.

However, with the presence of DP layer at the drain side region, the PBT effect has been suppressed for VDS ≤ 2.5V. For VDS > 2.5V, the PBT effect has been minimized to a minimum level as the δp+ layer cannot contain with the surge of holes current due to higher II rate. Nevertheless, most of the device application operation voltage is below 2.5V which merit the incorporation of DP layer into the device.

Carrier mobilities in strained SiGe layer are different from Silicon as a result of local distortion due to the strain effects. It also contributes to the alloy scattering on the carriers [23]. The mobilities in strained layer is also depends on the transport direction, either parallel to the original SiGe growth interface or in the perpendicular direction [24-25]. Due to the splitting of the valleys in conduction band into lower four-fold and higher two fold states, the electron mobility becomes dependent on the in-plane and out-of plane directions. In the in-plane direction (in the plane of growth), the heavy longitudinal electron mass leads to lower electron mobility, while, in the out-of plane direction (out-of plane growth), the effective electron mass is reduced and hence, the mobility increases. The higher doping levels also contribute to increase in electron mobility due to ionized impurity scattering.

Figure 4 shows the carrier concentrations (electron and hole) in different regions of the device. It can be seen that the electron concentration at the source end is higher than the hole concentration. This is due to the presence of n-type Antimony dopants in the substrate. Hole concentration are at peak in δp+ layer region as high doped boron concentration is imperative to create pn junction separating n-type source and drain.

Fig. 4. Carrier Concentraion of VESIMOS-DP for Si0.7Ge0.3, S/D doping =2.0x1018/cm3, VDS=1.75V.

In VESIMOS-DP, the electrons are transported towards the drain end and the holes are transported in the opposite direction towards the source end [16]. On application of bias, the electrons cross the p-type triangular barrier are transported towards the drain, thus forming ON current of the device. The holes generated during the impact ionization process charge the floating p-body and are transported towards the source end. This can be seen in the graph where a huge spike of hole concentration in δp+ layer region and higher concentration level at the source side compared to the drain side region. Electrons are the majority carries in VESIMOS-DP which is transported through drift mechanism. That’s why the drift current mechanism of carrier transport is seen in VESIMOS-DP.

A comparison between the electron mobility profiles of VESIMOS and VESIMOS-DP were done as shown in figure 5. It can be observed that the electron mobility is higher in the VESIMOS-DP compared to VESIMOS. The electron mobility in the VESIMOS-DP (~1440m2/V-s), was found to be increased by 4% in comparison to VESIMOS (~1386 m2/V-s) which is not a very significant improvement. The channel mobility of the device is primarily determined by the carrier scattering at the strained-Si/SiGe interface. The higher doping levels also contribute to increase in electron mobility due to ionized impurity scattering [24]. However, alloy scattering in the strained SiGe layer, tends to affect the electron mobility [25]. Hence, as seen in figure 5, the mobility in the strained layer increases to a maximum value and then decreases. This is due to the alloy scattering of SiGe. However with the vicinity of DP, the mobility decreases is little less when compared to VESIMOS which proof the alloy scattering are reduced in VESIMOS-DP.

Breakdown Region

Fig. 5. Comparison of electron mobility profiles of VESIMOS and VESIMOS-DP for Si0.7Ge0.3, S/D doping =2.0x1018/cm3, VDS=1.75V.

In addition, it can also be seen from the graph that the peak electron mobility is in the intrinsic-Si region. This is because the intrinsic-Si cap layer is very thin (5nm), which does not relieve strain as soon as the electron comes out of the strained SiGe layer. Hence, the Si cap layer must be thick enough to relive the strain on electrons. But increasing the thickness of Si cap layer means that the SiGe layer has to be moved closer to the δp+ layer. Doing so, would cause boron diffusion into the SiGe layer, which would alter the device characteristics. In vertical structures, as the carrier transport is in the out-of plane direction, both electron and hole mobility enhancement can be seen in the compressively strained SiGe layer [24]. However, no significant enhancement of hole mobility was seen as the holes are the minority carriers and they are mostly confined to the delta-p layer.

IV. CONCLUSION The advantages of incorporating dielectric pocket (DP) that

leads to the improvement of carrier mobility to the Vertical Strained-SiGe Impact Ionization MOSFET device has been investigated and explained. The dependency of the strain SiGe and DP size on the device performance is shown using Sentaurus TCAD tools. Due to the DP layer, the electron mobility in the VESIMOS-DP (~1440m2/V-s) was found to be increased by 4% in comparison to VESIMOS (~1386 m2/V-s) device which is not a very significant improvement. The mobilities in strained layer is depends on the transport direction, either parallel to the original SiGe growth interface or in the perpendicular direction. Carrier mobilities in strained SiGe layer are different from Silicon as a result of local distortion due to the strain effects. It also contributes to the alloy scattering on the carriers. However with the vicinity of DP, the carrier scattering effect has reduced which merits the introduction of DP on the device. The threshold voltage, VTH and subthreshold voltage, S was found to be stable across various DP size from 20nm to 80nm justified the vicinity of the DP on improving the performance of the device.

ACKNOWLEDGMENT The authors would like to acknowledge the financial

support from ERGS (ERGS0002-TK-1/2011) fund of MOHE and E-Science fund (03-01-10-SF0175) of MOSTI Malaysia. The author is thankful to the University Malaysia Sabah (UMS) for providing excellent research environment in which to complete this work.

REFERENCES

[1] Troutman, R. R. (1979). VLSI limitations from drain-induced barrier lowering. IEEE Journal of Solid-State Circuits, 14(2), 383–391. doi:10.1109/JSSC.1979.1051189

[2] Gopalakrishnan K, Griffin PB, Plummer JD, “ I-MOS: a novel semiconductor device with a substhreshold slope lower than kt/q,” In: IEEE tech dig IEDM; 2002. p. 289–92.

[3] Gopalakrishnan K, Griffin PB, Plummer JD, “Impact ionization MOS (I-MOS) –part I: device and circuit simulations”, IEEE Trans Electron Dev2005;52(1):69–76.

[4] Gopalakrishnan K, Woo R, Jungemann C, Griffin PB, Plummer JD,” Impact ionization MOS (I-MOS) – part II: experimental results”, IEEE Trans Electron Dev 2005;52(1):77–84.

[5] Choi WY, “ Effect of device parameters on the breakdown voltage of impact ionization metal–oxide–semiconductor devices”, Jpn J Appl Phys, 2009;48:040203-1–3-3.

[6] Choi WY, “Applications of impact-ionization metal–oxide-semiconductor (I-MOS) devices to circuit design”, Current Applied Physics 10 (2010) 444–451

[7] Charbuillet C, Monfray S, et al, “ High current drive in ultra-short impact-ionization MOS (I-MOS) devices”, In: IEDM; 2006. p. 1–4.

[8] Onal C, Woo R, Koh H-Y, Griffin P, Plummer J. A novel depletion-IMOS (DIMOS) device with improved reliability and reduced operating voltage”, IEEE Electron Dev Lett 2009;30(1):64–7.

[9] Savio A, Monfray S, Charbuillet C, Skotnicki T, “On the limitations of silicon for IMOS integration”, IEEE Trans Electron Dev 2009;56(5):1110–7.

[10] Abelein U, Born M, et al, “A novel vertical impact ionization MOSFET (I-MOS) concept,” In: Proc 25th international conference on microelectronics (MIEL ’2006), Niš, Serbia; 2006. p. 127–9.

[11] Abelein U, Born M, et al, “Improved reliability by reduction of hot-electron damage in the vertical impact-ionization MOSFET (I-MOS),” IEEE Electron Dev Lett 2007;28(1):65–7.

[12] Abelein U, Assmuth A, et al, “Doping profile dependence of the vertical impact ionization MOSFET’s (I-MOS) performance,” Solid-State Electron 2007;51:1405–11.

[13] Abelein U, Assmuth A, Iskra P, et al, “Vertical 40 nm impact ionization MOSFET (I-MOS) for high temperature applications,” In: Proc 26th international conference on microelectronics (MIEL ’2008), Niš, Serbia; 2008. p. 287–90.

[14] M. Schlosser, P. lskra. U. Abelein. H. Lange , et al , “The Impact Ionization MOSFET (IMOS) as low-voltage optical detector ,” Nudear Instrumenm and Methods in Physics Rerearch A 524 (2010) 524-527.

[15] Kraus R, Jungemann C, “Investigation of the vertical IMOS-transistor by device simulation,” In: Proc ULIS, international conference on ultimate integration of silicon, vol. 10; 2009. p. 281–4.

[16] Dinh TV, Kraus R, “Investigation of the performance of strained-SiGe vertical IMOS-transistors,” In: Proc ESSDERC; 2009. p. 165–8.

[17] Thanh Viet Dinh, Christoph Jungemann, “Impact ionization rates for strained Si and SiGe,” Solid-state Electronics 53 (2009) 1318-1324

[18] Ismail Saad, Divya Pogaku, et al, “Enhanced Performance Analysis of Vertical Strained-SiGe Impact Ionization MOSFET (VESIMOS),” Semiconductor Electronics (ICSE), 2012 10th IEEE International Conference, Kuala Lumpur, Malaysia.

[19] Ismail Saad, Mohd. Zuhir H., et al, “Investigation of Incorporating Dielectric Pocket (DP) on Vertical Strained-SiGe Impact Ionization MOSFET (VESIMOS-DP),” Semiconductor Electronics (ICSE), 2012 10th IEEE International Conference, Kuala Lumpur, Malaysia.

[20] S. K. Chun and K. L. Wang, “Effective mass and mobility of holes in strained Si Ge layers on (001) Si Ge substrate,” IEEE Trans. Electron Devices, vol. 39, pp. 2153–2164, Sept. 1992.

[21] J. M. Hinckley and J. Singh, “Hole transport theory in pseudomorphic Si Ge alloys grown on Si (001) substrates,” Phys. Rev. B, vol. 41, no. 5, pp. 2912–2926, 1990.

[22] M. Jurczak, T. Skotnicki, et al, “Dielectric Pockets – A New Concept of the Junctions for Deca-Nanometric CMOS Devices,” IEEE Trans. Electron Devices, 48(8):1770–1775, August 2001.

[23] Zoolfakar, A.S., and Ahmad, A.,“Hole mobility enhancement using Strained Si, SiGe technology,” 5th International Colloquium on Signal Processing & Its Applications (CSPA), 4-6 March 2009.

[24] Xiangdong Chen, Kou-Chen Liu, Qiqing Christine Ouyang, Sankaran Kartik Jayanarayanan and Sanjay Kumar Banerjee, “Hole and Electron Mobility Enhancement in Strained SiGe Vertical MOSFETs,” IEEE Transactions On Electron Devices (IEDM) 2001., 48(9):1975-1980.

[25] Fischetti, M. V. and Laux, S. E.” Band structure, deformation potentials and carrier mobility in strained Si, Ge and SiGe alloys,” Journal of Applied Physics, 80(4): 2234-2252. 1996

[26] Sentaurus user Guide Device and Process SimulationSoftware, Sentaurus Inc, 2012.