ICSE2006 Proc. 2006, Kuala Lumpur, Malaysia

Physical-Based SPICE Model of CMOSSTI y-Stress Effect

Philip Beow Yew Tan1' 2, Albert Victor Kordesch1 and Othman Sidek21Silterra Malaysia Sdn. Bhd. Kulim Hi-Tech Park,09000 Kulim, Kedah, Malaysia2University Science Malaysia, 14300 Nibong Tebal, Pulau Pinang, Malaysia

*Email: philip tangsilterra.com

Abstract - In this paper, we proposed a newphysical-based equation to model the CMOStransistor STI y-stress (in the direction ofchannel width). It can be used in any SPICEMOS model and it has been verified on0.13um CMOS transistors. The physicalcharacteristics of the compressive STI y-stresseffect on saturation drain current, Idsat arecaptured by using a new proposed transistorlayout method. The equation that is able todescribe the physical characteristics of theSTI y-stress effect is incorporated into theelectron and hole mobility, uO of the SPICEmodel to capture the y-stress effect on Idsat.With the combination of the new y-stressparameters and the default delta widthparameters in the SPICE model, we are ableto fit the simulation curve to the hook shapedIdsat curve from the actual silicon data.

I. INTRODUCTION

STI stress effect is a hot issue nowadays andmany researchers have put much effort into thissubject [1, 2, 3, 4]. The great interest on thissubject is mainly driven by the fact that stresschanges the mobility of electrons and holes inCMOS transistors and it is unavoidable becausethe stress is built-in to the fabrication process.The explanation for this phenomenon is theeffective mass of electron and hole changesbecause the shape of the conduction bandchanges due to stress on the silicon latticestructure and the number of carriers in variousbranches of the conduction band changes due toenergy level shifts [2]. Another phenomenon isthe mechanical stress causes the dopant diffusionto change that later changes the electricalcharacteristics such as threshold voltage of thefinished transistor [3].

The effect of STI stress in the direction ofchannel length has been captured in the lateststandard SPICE model by using Sa and Sb

(Space of active). Since STI stress is a 2-Deffect, the compressive stress in the direction ofchannel width also changes the drain current of atransistor. Hence, in this study we proposed aphysical equation that will be added into thecarrier mobility equation, uO to capture the effectof compressive STI stress effect in the directionof channel width (y-stress).

In the standard SPICE models, the delta width(DW) effect will raise the saturation drain current(Idsat) of narrow width transistors. We proposeto add in the effect of compressive STI y-stressto uO which will degrade the Idsat of narrowwidth transistors because of the reduction inmobility due to compressive y-stress. Thecompressive y-stress degrades both the NMOSIdsat and PMOS Idsat [1]. The combination ofboth the DW effect and the mobility degradationdue to compressive STI stress will result in ahook shaped Idsat versus width curve as seen inthe actual silicon measurement data, as shown inFig. 1.

14 F0

13.0 -

12.0,-Amount ofIdsat dropE 11.0-

S- 100. - HI1ook Shaped Idsat Cure

X9.0- t80- Minimrlnum Value

7.0 - NMOS, L = 10um

60-0 2 4 6 8 1 0 12

Width (um)

Fig. 1 Actual silicon measured data showing a hookshaped Idsat vs Width curve.

We have demonstrated the hook shaped Idsatcurve in our previous study in [5] and we haveproposed an empirical SPICE model to capturethe hook shaped Idsat curve in [6]. In this paper,we propose a physical-based SPICE model that isable to capture the physical behavior of the hookshaped Idsat curve correctly and accurately.

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ICSE2006 Proc. 2006, Kuala Lumpur, Malaysia

II. EXPERIMENTAL STRUCTURES

The CMOS transistor structures used in thisexperiment are categorized into 2 groups. Thefirst group is for extracting the characteristics orbehavior of the STI y-stress effect on draincurrent in saturation, Idsat. The second group isto verify the new physical-based model withbuilt-in STI y-stress effect.

For the first group of experimental structures,we use a standard W/L = 1Oum/0. 13um transistorlayout. We shrink the Select layer to form thechannel width of 0.5um and step through the10um channel from the edge of the channelwidth to the middle of the channel (total 10steps). This means that we actually built 10transistors with W/L = 0.5um/0.13um but eachof them will have different distance of channelwidth to STI edge. This enables us to evaluatethe compressive STI y-stress on transistorchannel width. We have proposed this method ofevaluating the STI y-stress in [7].

The second group of experimental structuresare transistors with two fixed lengths, 10um and0.13um, and eight different widths varying from0.15um to 1Oum. These structures will enable usto plot the Idsat versus width curve for both longand short channel length transistors.

All the transistors in this experiment arefabricated using Silterra's standard 0.13umCMOS technology. The linear threshold voltage(Vtlin) is extracted at Id = 0. 1uA*(W/L) with Vd= 0.1V and Vs = Vb = OV. Saturation draincurrent (Idsat) is extracted at Vg = Vd = 1.2Vand Vs = Vb = OV. The operating voltage (VDD)for this 0.13um technology is 1.2V.

III. PHYSICAL CHARACTERISTICS

By using the first group of experimentalstructures, where we step through the 1 Oumchannel from the edge of the channel width to themiddle of the channel (total 10 steps) using0.5um wide Select implant layer, we are able toavoid (or reduces) the compressive STI y-stresson the transistor edge. When the Select implantlayer is coincident with the STI edge (Oum indistance) the transistor will have the highest y-stress effect. When the transistor is 4.5um awayfrom the STI edge, we assume the transistor is y-stress free.

From our study in [7], we found that theamount of Idsat decrease is caused by the STI y-stress effect. Hence, we know that the percentageof Idsat decrease is proportional to the intensity

or amount of compressive STI y-stress effect onthe transistor. Fig. 2 shows that the compressiveSTI y-stress effect on NMOS transistor is afunction of distance from STI edge and can beroughly described by using an exponentialrelation as in Equation 1 (shown by the brokenline). By adding a new parameter B, we can havea better-fit curve to the data as shown by thesolid line, Equation 2. The STI y-stress effect onPMOS transistor shows similar characteristics toNMOS transistor (as shown in Fig. 3).

(1)y=A (e )y =A (eB3

By using the two parameters, A and B (as inEquation 2), we can have a better curve fit to theactual silicon data, as shown in Fig. 2 and Fig. 3.A is the multiplier parameter to control themaximum value of the curve and B is the powerparameter that controls the curvature of thecurve. If we were using the exponential curve,we can only control the maximum value of thecurve (as shown by the broken line) but cannotfit the curvature of the actual data.

120

0 8%- \(U

En% \ y = A (e )4%

2%-yA ~e)O 1 2 3 4 5

Distancejfrom_STI_Edge (um)Fig. 2 STI y-stress effect on NMOS transistor. Thepercentage of Idsat decrease is equivalent to theintensity of STI y-stress effect on the transistor.

4q(A

L-

Cu

~0

4U)'aoz

1 2%-

10% 4

8%

G%

4%

u o

-2%

-4%-J

-6%Distance_from_STI_Edge (um)

Fig. 3 STI y-stress effect on PMOS transistor. Thepercentage of Idsat decrease is equivalent to theintensity of STI y-stress effect on the transistor.

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(2)

ICSE2006 Proc. 2006, Kuala Lumpur, Malaysia

IV. SPICE MODEL

Since the effect of STI y-stress is higher fornarrower channel width, we can rewrite Equation1 and Equation 2 as a function of channel width,W, as shown in Equation 3 and Equation 4. Wemodify the electron and hole mobility, uO in theSPICE model to incorporate the effect of STI y-stress into the model based on Equation 3 andEquation 4.

f(W) =A .(ew)3f(W) =A .(e

(3)

(4)

Fig. 4 and Fig. 5 compare the fitting ofstandard model (default uO), exponential model(uO incorporated with Equation 3) and y-stressmodel (uO incorporated with Equation 4) to theactual silicon data for NMOS, L = 10um and0.13um. Similar comparison plots for PMOS areshown in Fig. 6 and Fig. 7.

The actual data in Fig. 4 is the same data as inFig. 1 that has the hook shaped curve. In Fig. 4 toFig. 7, we plotted the x-axis in log scale to zoominto the narrow width transistors.

The standard model shows the delta width(DW) effect that raises the Idsat at narrow width,as shown by the dotted line. The broken linewhich represents the exponential model, hasmuch better fitting compared to the standardmodel. The solid line (y-stress model) shows aneven better fitting to the measured data comparedto exponential model, which can be clearly seenin Fig. 4. and Fig. 6. The difference of theexponential model and y-stress model is hardlyseen in Fig. 5 and Fig. 7. This is because in Fig.5 and Fig. 7, the exponential model alreadyprovides a good fit to the actual data and notmuch we can fine-tune in the y-stress model.

18.0Data

16.0~~~~~~~~~~~~----Std_Model140 - Exp Model

-y-Slress Model12. 0 -12.0i ----:

X 10.0

6.00.1 1 10

Width (um)Fig. 4 Plot of Idsat versus Width for NMOS, L=lOum.This plot compares the fitting of standard model,exponential model and y-stress model to the actualsilicon data.

0.1 1 10

Width (um)Fig. 5 Plot of Idsat versus Width for NMOS,L=0.13um. This plot compares the fitting of standardmodel, exponential model and y-stress model to theactual silicon data.

5.0

4.5- + Data _------ Std Model

3 4.0- -Exp Model

3y-Stress_Model

3 30-_u ** ---- ---------

-r

2) I

0.1 1 10

Width (um)Fig. 6 Plot of Idsat versus Width for PMOS, L=lOum.This plot compares the fitting of standard model,exponential model and y-stress model to the actualsilicon data.

260.6 280 0 - + ~~~~~~~~~~~Data .

2600 ------- Std_ModelA 240.0 -Exp_ModelE 220.0 -y-Stress6ModelcX 200.0180.06-

160.6X 160.6140.0 -

120.0 - PMOS, L = O.13um1 60.6

0.1 1 10

Width (um)Fig. 7 Plot of Idsat versus Width for PMOS,L=0.13um. This plot compares the fitting of standardmodel, exponential model and y-stress model to theactual silicon data.

Theoretically, Equation 4 will give moreflexibility to fine-tune the hook shaped Idsatcurve compare to Equation 3. Together with theDW effect parameter (wint) in SPICE model,

757

800 075.0

- 7000 -

EI

65062 6000 -

x 550.0

- 500.0

45.04000

# Data------ Std_Model--Exp Model

y-Gtress_Model

NMOS, L = 0.13um

PMOS, L = 10um

NMOS, L = 10um

ICSE2006 Proc. 2006, Kuala Lumpur, Malaysia

Equation 3 can only control the amount of Idsatdrop with the minimum fixed value in width(Refer to Fig. 1 for the illustrations of "amountof Idsat drop" and "minimum value").

By using Equation 4, we are able to controlboth the amount of Idsat drop and also to movethe minimum value of the Idsat to fine-tune thehook shaped curve. From Equation 4, parameterA is used to control the amount of Idsat drop forthe hook shaped curve vertically and parameter Bis used to move the minimum value of the hookshaped curve horizontally, as illustrated in Fig. 8.

1 2

3 11.0 -

.2 10.0-

w 9.0 -

8 0 -

7.0 -

Electron Devices, TED, vol.5 1, no.8 (2004).[3] Y-M. Sheu et al., "Modeling Mechanical Stress Effect

on Dopant Diffusion in Scaled MOSFETs," IEEETransactions on Electron Devices, TED, vol.52, no.1(2005).

[4] K-W. Su et al., "A Scalable Model for STI MechanicalStress Effect on Layout Dependence of MOS ElectricalCharacteristics," Custom Integrated CircuitsConference, CIC, pp. 245-248 (2003).

[5] P. B. Y. Tan et al., "Hook Shaped Drain Current vsWidth Curve of 130nm CMOS Technology," NationalSymposium on Microelectronic, NSM, (2005).

[6] P. B. Y. Tan et al., "Compact Modeling of Mechanicaly-Stress Effect," International Conference on Solid-State and Integrated Circuit Technology, ICSICT,(2006).

[7] P. B. Y. Tan et al., "Measuring STI Stress Effect onCMOS Transistor by Stepping through the ChannelWidth," 2006 International of RF and MicrowaveConference, RFM, (2006).

0 2 4 6 8 10 12Width (um)

Fig. 8 Illustration of how the parameter A andparamter B in the y-stress model control the hookshaped Idsat curve. W is the channel width.

V. CONCLUSION

In conclusion, we have proposed equationthat is able to capture the physical characteristicof the compressive STI y-stress effect on NMOSIdsat and PMOS Idsat. By incorporating thisequation into the mobility parameter, uO, we areable to model the y-stress effect on Idsat.Together with the DW effect parameter, we areable to model the actual behavior of the hookshaped Idsat curve correctly and accurately.

ACKNOWLEDGEMENT

The authors would like to acknowledge all themembers of Silterra Malaysia Sdn. Bhd. forsupporting and contributing to the research workin this paper.

REFERENCES

[1] C. H. Ge et. al., "Process-Strained Si (PSS) CMOSTechnology Featuring 3D Strain Engineering,"International Electron Device Meeting, IEDM, pp.73(2003).

[2] C. Gallon et al., "Electrical Analysis of MechanicalStress Induced by STI in Short MOSFETs UsingExternally Applied Stress," IEEE Transactions on

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Parameter A

Hook Shaped Idsat Clurve

Parameter B

Equation: f(W) =A ;- )

14 11,

h 11