ICSE2006 Proc. 2006, Kuala Lumpur, Malaysia

Design of 1 OOnm Single-Electron Transistor (SET) by 2DTCAD Simulation

aAmiza Rasmi, bUda Hashim, aAbdul Fatah Awang Mat

aMicroelectronics & Nano Technology Unit, Telekom Research and Development Sdn. Bhd.,Idea Tower I, UPM-MTDC, Technology Incubation Centre One, Serdang, Selangor, Malaysia

bKolej Universiti Kejuruteraan Utara Malaysia, Perlis, MalaysiaEmail:

Abstract One of the great problems in currentlarge-scale integrated circuits (LSIs) isincreasing power dissipation in a small siliconchip. Single-electron transistor (SET) whichoperate by means of one-by-one electrontransfer, small size and consume very lowpower are suitable for achieving higher levels ofintegration. In this paper, SET is designed with100nm gate length and 10nm gate width issuccessfully simulated by Synopsys TCAD. Thepower of SET device that obtained fromsimulation is 3.771 x 10-9 Watt for fixed currentand 3.3565 x 10-9 Watt if fixed the gate voltage,VG, and the capacitance of this device is 0.4297aF. These results were achieved at roomtemperature operation.

I. INTRODUCTION

Single-electron transistor (SET) is a keyelement in single electronics where deviceoperation is based on one-by-one electronmanipulation utilizing the Coulomb blockadeeffect and can be made very small (nanometerscale). However, SET has low voltage gain, highinput impedances, and is sensitive to randombackground charges [1]. This makes it unlikely thatSET would ever replace field-effect transistors(FETs) in applications where large voltage gain orlow output impedance is necessary.

SETs can potentially take the industry allthe way to the theoretical limit of electrons forcomputing applications by allowing the use of asingle electron to represent a logic state [2]. Thefirst application for SET could be for the memoryand special applications in metrology, such asprimary thermometers and supersensitiveelectrometers [2].

In this paper, some introduction of single-electron transistor (SET) is discussed in the nextsection. The process and device simulation is thendiscussed in the section 3, before concluding.

II. SINGLE-ELECTRON TRANSISTOR (SET)

The most fundamental three-terminalsingle-electron devices (SEDs) are called single-electron transistor (SET) [3-5]. SET is alwaysthree-terminal devices with gate, source, and drainas shown in Figure 1, unlike quantum dots (QDs)and resonant tunneling devices (RTDs) which maybe two terminal devices without gates [6]. TheSET is expected to be a key device for futureextremely large-scale integrated circuits because ofits ultra-low power consumption and small size.

T'sUnd GateFGt ILSET xsadG<lTisland

So~~irce(9 ai Source Drn802 \

in

Tunnelbanrer Tunnel barrier(tunnel capacior) (tnnel capacitor)

Figure 1: Schematic structure and equivalent circuit of asingle-electron transistor (SET) [7]

As shown in the Figure 1, the device musthave a small island together with a gate electrodecoupled to the island with gate capacitance, Cg.Source and drain electrodes are attached to theisland via a tunnel barrier. In addition, SET is adevice whose operation relies on single electrontunneling through a nanoscale junction. Theoperation principle of SET is shown in Figure 2.

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ICSE2006 Proc. 2006, Kuala Lumpur, Malaysia

source dIrain source drain

000 -0

Figure 2: Transfer of electrons is (a) one-by-one inSingle Electron Transistor (SET), which is incontrast with (b) conventional MOSFET wheremany electrons simultaneously participate to thedrain current [8-9].

From Figure 2, many electrons (1000-10,000 electrons) [10] simultaneously participate fromthe source to the drain current in the conventionalMOSFETs. On the contrary, the electrons in SETdevices are transferred one-by-one through thechannel [11]. These features are suitable forachieving higher levels of integration. In addition,SET has unique features that conventional MOStransistors do not have. The first one is SET canhave many gates (gate and back gate) [11]. Theother one is oscillatory conductance as a functionof a gate voltage [12]. Therefore, it is generallyassumed that single-electron devices have potentialto be much faster than conventional MOSFETs.

III. RESULTS AND DISCUSSION

Process and device simulation iscommonly use for the design of new very largescale integration (VLSI) devices and processes.Simulation programs serve as exploratory tools inorder to gain better understanding of process anddevice physics [13]. In this research, the SynopsysTCAD tools Taurus TSUPREM-4 [14] andMEDICI [15] is utilized for process simulation anddevice simulation.

The process simulation is to define theSET device structure and process parameter. In theprocess simulation, the mask layout is become asan input data. The mask layout consist of fourmask layers namely source layer, polysilicon gatelayer, contact layer, and metal layer as shown inFigure 3.

Figure 3: Mask layout

Figure 4: Cross-section view of SET device

Figure 4 shows the cross-section of SETdevice with the gate length is 100nm and the gatewidth is 10nm. The four electrodes such as source,drain, gate and substrate is defined.

The device simulation is to define thedevice characteristics such gate characteristics anddrain characteristics. The output data from theprocess simulation is used as an input data fordevice simulation. This device simulation is doneby using the Taurus Medici.

For gate characteristic, the drain current, IDas a function of the gate voltage, VG is shown inFigure 5.

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ICSE2006 Proc. 2006, Kuala Lumpur, Malaysia

Figure 5: Drain current, ID as a function of the gatevoltage, VG-

Here, the drain voltage was 1 mV, the source andsubstrate (back gate) voltages were fixed at 0 Vand the device temperature was 300K.

As shown in Figure 11, the graph isdivided into three sections. In section A (from VGat 0 V to VG = 0.4 V), the drain current is increasedimmediately. At VG = 0. 4 to VG = 0.7 V (sectionB), the drain current increased linearly. While, inthe section C when VG is 0.7 V to 2.0 V, the draincurrent increased slowly.

Additionally, this graph is also given someinformation about this device. Firstly, the linearslope of this exponential graph is calculated. Thelinear slope is given by

dy Y2 YIdxx2 X1

From the ID VG graph (Figure 5),

(1.1)

R- -G IMV/A=-4.1904&1cPQID 2.386X10- 6xO..In

From the calculation, the SET device resistance, Ris 4.1904 x 106 Q. The power, P of SET device isgiven below,

P = VI (1.3)

From Equation (1.2), V = IR, so the power is

P = I2R (1.4)

From ID-VG graph as shown in Figure 5, let say I3.0 x 10-7 A/pm hence

3.OX10 7A x0. Im)2]X[4.1904x106 Q]

P = 3.771x 10-9 Watt

The power, P for SET device is 3.771 x 10-9 Wattfor a fixed current. If voltage is fixed, let say V=0.5 V, I= 2.8302 x 10-7 A/prm (get from Figure 5)andR =4.1904x 106 Q,

p (2.8302X10 AXO.Im)2]x[0.4190x106 Q]

P = 3.3565x10-9Watt

So, power, P =3.3565 x 10-9 Watt. From the twocalculations of power, the power, P of SET deviceis very low (10-9 Watt).The threshold voltage, VTH is the minimum valuerequired for tunneling as shown below [16,17]

vt Ceth C (1.5)

dy (5.216601 7-2.8303x10)A/pM 2386X106Adx (0.6-0.5)V

From this calculation, the linear slope is 2.386z10-6 A/JmV. From the Ohm law,

V =IR, (1.2)

From Equation (1.5), the capacitance, C of SETpm device can be calculated. From the ID VG graph,

VTH= 0.3728 V at VG= 0.5 V and e = 1.602 x 10-19a x C. Hence, the capacitance, C is

C e = 1.602 x 10 19C0 18C = - =0.4297xl F

VTH 0.3728V

the resistance, R of SET device can be calculated.Based on the Ohm law, the resistance, R is

The calculation showed capacitance, C =

0.4297xlO-18 F or 0.4297 aF. As a result, the

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ICSE2006 Proc. 2006, Kuala Lumpur, Malaysia

capacitance, C from the simulation result is 0.4297aF at 300 K. Based on the previous experimentalresult done by Wasshuber, the capacitance, C is 3aF at 300 K [18]. Another result done byTakahashi et.al. [19] is C = 2 aF at roomtemperature. Compare to two of the three results,the result from the simulation is smaller than theprevious experiment done by others.The charging energy, Ec for SET is given below,

e2EC= (1.6)

From Equation (1.5), C = 0.4297 x 10-18 F. Hence,the charging energy for this system is

E (1.602x10-19)22(0.4297 x 10- 18)2.9863 x 10- 20

-eV1.602x10-19

Ec = 0.1864eV = 186.4meV

The calculation showed the charging energy, Ecfor SET system is 186.4 meV at 300 K. Based on

the previous reported about SET [20]; the chargingenergy is increased to 173 meV, which means thatthe transistor is able to operate at 300K. As a

result, the value of charging energy from thiscalculation is nearly to the previous reported.Hence, the SET in this project is operated at 300 K.

In addition, the threshold voltage at 0.600V gate bias is 0.3728 V and the channel length ofthe SET device is 61.27 nm. The simulation resultshows that the sub threshold slopes for SET at 0.10V gate bias is 112.3 mV/decade. The leakagecurrent (IOOF) at 0.0 V gate bias is 4.1715 x 10-12A/lm and the drive current, ION is 0.034 iA/im atVG = VD = 1.5 V.

For drain characteristic, the drain current,ID as a function of the drain voltage, VD is shown inFigure 6. Here, the gate voltage, VG was 1.5 V, thesource and substrate (back gate) voltages were

fixed at 0 V and the device temperature was 300 K.

Figure 6: Drain current, ID as a function of thedrain voltage, VD.

Drain OCnent vs Drain Voltage

Figure 7: Drain current, ID as a function of the drainvoltage, VD at various gate voltages, VG.

Figure 7 shows the drain current as a

function of a drain voltage at various gate voltages,VG. From the graph, increasing the gate voltage, VGthe drain current, ID will also increased. Thesaturation occurred at VD = 0.30 V to VD = 2.0 V.

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ICSE2006 Proc. 2006, Kuala Lumpur, Malaysia

200

1 50

1-25

0.:75

-0.25

1.75 ;SO - SETT = 3SEK

V. = 4V

0 P . I , L - E . I . f . I .... ........... I S. I0.0 0-5.5 i0 1 s 2O 2.5 3ac 3 5 4.0

Vd6 (V)

Figure 8: The ID- VD characteristics for differentvalues of the gate voltage at 300 K [21].

Figure 7 and 8 shows the ID VD characteristics atvarious gate voltage, VG and temperature at 300Kare obtained from simulation and previousexperiment. The curve from the simulation is quitesimilar to the previous experiment.

IV. CONCLUSIONS

Among various single-electron devices(SEDs), the single-electron transistor (SET) is themost fundamental. The SET simulation issuccessfully simulated using Synopsys TCADsimulation tools.

From the simulation, the threshold voltagefor SET device is 0.3728 V and the channel lengthis 61.27 nm. The SET device is operated at 300K(room temperature operation). From thecalculation, the charging energy, EC of SET systemis 186.4 meV. The capacitance, C of SET device is0.4297 aF and the power, P of SET device is 3.771x 10-9 Watt for fixed current and 3.3565 x 109Wattif fixed the gate voltage. The power, P of this SETdevice is obtained from the ID-VG graph with fixedthe resistance, R. The resistance, R is 4.1904 x 106Q.

The value of capacitance that obtained inthis simulation is smaller than the previousexperiment and the charging energy is higher thanthe previous reported. Ultimately, this research hasutilized the process and device simulation tools asan alternative for an actual SET fabricationprocess.

ACKNOWLEDGEMENT

The authors would like to thankNorthern Malaysia University CollegeEngineering and Government of Malaysiagranted this project through IntensificationResearch in Priority Areas (IRPA).

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