Compact Modeling of Mechanical STI y-Stress Effect Philip Beow Yew Tan1,2 *, Albert Victor Kordesch1 and Othman Sidek2

1Silterra Malaysia Sdn. Bhd. Kulim Hi-Tech Park,09000 Kulim, Kedah, Malaysia 2University Science Malaysia, 14300 Nibong Tebal, Pulau Pinang, Malaysia

*Email: philip_tan@silterra.com

Abstract

In this paper, we proposed two new MOS compact model parameters (synu0 and sypu0) to be added to the mobility parameter u0 to model the mechanical shallow trench isolation (STI) y-stress. By using a layout experiment, we show that the STI y-stress causes the hook shaped Idsat versus width curve. We demonstrate that by introducing these new model parameters, we are able to fit the actual data more accurately. The STI y-stress effect is modelled by using the synu0 parameter (for NMOS) and sypu0 parameter (for PMOS) to control the fit to the hook shaped Idsat curve.

1. Introduction

As the technology nodes scale down, compact modeling efforts become more and more challenging. More equations and parameters need to be added to the existing compact models to accommodate the new effects that appear (or become significant) as transistor size keeps shrinking down to deep submicron nodes. One of the important effects of the deep submicron CMOS transistors is the mechanical STI stress effect. This effect has been extensively studied in the current literature [1-3] and Sa and Sb parameters have been added to the transistor netlist to enable the current BSIM4 model [4] to capture the mechanical STI stress effect in the direction of channel length (x-stress). From our previous experimental data on standard foundry 130nm CMOS technology, we found that only the long channel NMOS Idsat and the short channel PMOS Idsat (normalized to width) exhibit a hook shaped behavior when plotted against width. From our studies [5, 6] and the literature [7], we strongly believe that the hook shaped Idsat curve is caused by the STI y-stress (in the direction of channel width). The transverse compressive stress reduces the Idsat when channel width decreases to around 1um or less. This is opposite to the delta width (DW) effect that increases the Idsat when channel width goes farther below 1um. This explains how the hook shaped Idsat curve is formed.

Since the current compact model has no parameter to capture the hook shaped Idsat curve, we proposed two new parameters, synu0 and sypu0 to model the hook shaped Idsat curve for both NMOS and PMOS devices.

2. Experiment

The test structures used in this experiment are transistors with fixed L=0.13um, Sa=Sb=0.34um and varying the width from 0.15um to 10um. We have two set of transistors. Set 1 is with normal width, where the width is defined by active area (the standard way of defining the transistor width), as shown in Figure 1. Set 2 is with artificial width, where the width is defined by source-drain implant select layer. (non-standard way of defining transistor width), as shown in Figure 2. The transistors are fabricated using Silterra’s industry standard 130nm CMOS technology. In our measurement setup, saturation Id (Idsat) was measured at Vg=1.2V and Vd=1.2V. To normalize it we divide by the drawn width. Linear Vt (Vtlin) was measured at Vg=0.1*(W/L) and Vd=0.1V.

3. Results and Discussion

Figure 3 to Figure 6 show the model accuracy plots of Vtlin and Idsat for Set 1 (normal width) and Set 2 (artificial width) transistors with L=0.13um. For NMOS at L=0.13um (Figure 3 and Figure 4), STI y-stress effect has no significant effect on both Vtlin and Idsat. Also, no significant y-stress effect is seen on PMOS Vtlin at L=0.13um, as shown in Figure 5. For L=0.13um PMOS Idsat, the actual data in Figure 6 shows a hook shaped Idsat curve that cannot be model by the standard compact model. By using the model with STI y-stress effect, we can successfully capture the hook shaped Idsat curve. Since we do not have L=10um data in this experiment, we take our previous data from [5] for the model accuracy plots, as shown in Figure 7 to Figure 10. Figure 7 and Figure 8 demonstrated that the model with STI y-stress has a better fitting to the actual data in NMOS Vtlin and Idsat compared to the standard model. For L=10um PMOS, both the STI y-stress model or the standard model can fit the actual data, as shown in Figure 9 and Figure 10.

The u0 equations with y-stress effect are given in Equation 1 for NMOS and Equation 2 for PMOS. The two new parameters used to control the hook shaped Idsat are synu0 for NMOS and sypu0 for PMOS. For this experiment both synu0 and sypu0 is 1.3. When synu0 and sypu0 are zero, the default mobility values (u0_default) will be taken. We implement the synu0 and

1-4244-0161-5/06/$20.00 ©2006 IEEE

sypu0 in u0 (in BSIM3 model) by using sub-circuit.

NMOS u0='u0_default-(((sqrt(sqrt(abs((1/(log(W*1e6) +0.11373))))))-0.75)*(L*1e6)*synu0)' (1) PMOS u0='u0_default-(((sqrt(sqrt(abs((1/(log(W*1e6) +0.11373))))))-0.75)*(1/(L*1e6))*sypu0)' (2)

4. Conclusion

In conclusion, we have shown that the hook shaped Idsat versus width curve is caused by the mechanical STI y-stress (in the direction of channel width) by introducing the artificial width layout method. We also demonstrated that the mobility, u0 equations with STI y-stress effect is able to model the actual data (hook shaped Idsat curve) more accurately for long channel NMOS and short channel PMOS.

Acknowledgments

The authors would like to acknowledge all the members of Silterra Malaysia Sdn. Bhd. for supporting and contributing to the research work in this paper.

References

[1] P. R. Chidambaram et. al., “Fundamentals of Silicon Material Properties for Successful Exploitation of Strain Engineering in Modern CMOS Manufacturing,” IEEE Transaction on Electron Devices (TED), vol. 53, no. 5, pp. 944 – 964 (2005).

[2] C. H. Ge et. al., “Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering,” International Electron Device Meeting, pp.73 (2003).

[3] M. Miyamoto et al., “Impact of Reducing STI-Induced Stress on Layout Dependence of MOSFET Characteristics,” IEEE Transactions on Electron Devices, vol.51, no.3 (2004).

[4] X. Xi et al., “BSIM4.3.0 MOSFET Model User’s Manual,” University of California, Berkeley, pp.13.1 - 13.7 (2003).

[5] P. B. Y. Tan et. al., “Hook Shaped Drain Current vs Width Curve of 130nm CMOS Technology,” National Symposium of Microelectronic (NSM),(2005).

[6] P. B. Y. Tan et. al., “Analysis of Deep Submicron CMOS Transistor Vtlin and Idsat versus Channel Width,” Asia-Pacific Microwave Conference (APMC),(2005).

[7] C. Pacha et al., “Impact of STI-Induced Stress, Inverse Narrow Width Effect, and Statistical Vth Variations on Leakage Currents in 120nm CMOS,” Solid-State Device Research Conference (ESSDERC),pp. 397 - 400 (2004).

Figure 1. Transistor layout with normal width. The transistor channel is affected by the STI y-stress effect.

Figure 2. Transistor layout with artificial width. The transistor channel is not affected by STI y-stress effect.

Figure 3. Plot of NMOS Vtlin vs Width for L = 0.13um from 1 die data. Data is measured from the test structures

in this experiment with Sa=Sb=0.34um.

Figure 4. Plot of NMOS Idsat vs Width for L = 0.13um from 1 die data. Data is measured from the test structures

in this experiment with Sa=Sb=0.34um.

Figure 5. Plot of PMOS Vtlin vs Width for L = 0.13um from 1 die data. Data is measured from the test structures

in this experiment with Sa=Sb=0.34um.

Figure 6. Plot of PMOS Idsat vs Width for L = 0.13um from 1 die data. Data is measured from the test structures

in this experiment with Sa=Sb=0.34um.

Figure 7. Plot of NMOS Vtlin vs Width for L = 10um. Data is taken from previous study [5] with Sa=Sb=10um. Each dot is the average of 171 data. No available data for

transistors with artificial width.

Figure 8. Plot of NMOS Idsat vs Width for L = 10um. Data is taken from previous study [5] with Sa=Sb=10um. Each dot is the average of 171 data. No available data for

transistors with artificial width.

Figure 9. Plot of PMOS Vtlin vs Width for L = 10um. Data is taken from previous study [5] with Sa=Sb=10um. Each dot is the average of 171 data. No available data for

transistors with artificial width.

Figure 10. Plot of PMOS Idsat vs Width for L = 10um. Data is taken from previous study [5] with Sa=Sb=10um. Each dot is the average of 171 data. No available data for

transistors with artificial width.