ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

Design of 2.5V, 900MHz phase-locked loop (PLL) using0.25gm TSMC CMOS technology

Lee Ping Seng, Tun Zainal Azni Zulkifli, Norlaili Mohd Noh and Basir SaibonSchool of Electrical and Electronic Engineering, Universiti Sains Malaysia,

14300 Nibong Tebal, Seberang Perai Selatan, Pulau Pinang,MALAYSIA

E-mail: eezainalReng.usm.my. eelai1i@eng.usm.mv, basir@eng.usm.my

Abstract In this paper, a 2.5V, operating at900MHz phase-locked loop implemented in0.25pm TSMC CMOS process technology ispresented. A high speed PFD is implementedusing true-single-phase clock (TSPC)technique which manages to operate up to1.1GHz. VCO using ring oscillator with dual-delay path scheme is implemented to achieve900MHz operation frequency with widertuning range. The PLL manage to lock withinlOOns. The PLL implementation only needs 67transistors and consumes 23.81mW.

I. INTRODUCTION

Phase-locked loops (PLL) find wide applicationin wireless and communication systems, diskdrive electronics, high-speed digital circuits, andinstrumentation. PLL can be used for jitterreduction, skew suppression, clock recovery, andfrequency synthesis [I]. With the development ofintegrated circuits (IC), low cost and high qualityPLLs have become available and continue toplay an important roll in today's communicationdevices. The recent design trends of CMOSPLLs make emphasis on a high operationalfrequency, fast acquisition time, low phase noise,low voltage, low power, a wide tuning range, andhigh integration. In this paper, CMOS chargepump PLL is addressed and the building blocksare investigated. Section II discusses the Phase-Locked Loop Concept. Phase-FrequencyDetector, Voltage-Controlled Oscillators, andCharged-Pump and Loop Filter. Section IIIpresents the simulation of the blocks.

1. II. PHASE-LOCKED LOOP BLOCKS

A PLL (Phase-locked loop) is a device whichcauses one signal to track another one and keeps

the output signal synchronizing with thereference input signal in frequency as well as inphase. If a phase error builds up, a controlmechanism acts on the oscillator in such a waythat the phase error is again reduced to aminimum.The PLL building blocks consist ofphase-frequency detector (PFD), charge pump,loop filter or low-pass filter (LF) and voltage-controlled oscillator (VCO).Phase-frequency detector (PFD) or also known

as type 4 PFD is a phase comparator thatproduces an output signal whose dc value islinearly proportional to the difference betweenthe phase of the reference and feedback signal.PFD acts as a phase detector during lock andprovides a frequency-sensitive signal to aidacquisition when the loop is out of lock.The function of charge pump is to deliver a

charge or current proportional to phase error toloop filter in order to produce a control voltage tothe VCO. The loop filter mainly used to removeany noise and high frequency components fromthe output voltage of the phase detector thusgiving an average (dc) voltage. Therefore, chargepump and loop filter is used to transform thetiming information which is the up and downsignals from the PFD to analog quantity in lowfrequency control voltage to control the VCO.Besides, loop filter is the primary building blockthat determines the dynamic performance of theloop which includes the capture and lock ranges,bandwidth, and transient response. VCO is afrequency-modulated oscillator whoseinstantaneous output frequency is directlyproportional to its input control voltage.There are 2 conditions to lock. First, VCO

clock must equal to the reference clock. If it isnot equal, frequency acquisition will occur inorder to reduce the frequency difference betweenreference clock and VCO clock before enteringthe phase acquisition. Second, the phasedifference between reference clock and VCOclock has settled to a constant value. Therefore,

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ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

REFCLK

Figure 1: Type 4 PFD schematic.

both frequency acquisition and phase acquisitionmust be completed in order to lock.

Phase-frequency detector (PFD) acts as a phasedetector during lock and provides a frequency-sensitive signal to aid acquisition when the loopis out of lock.

Figure I shows the PFD schematic. PFD

compares the phase and frequency of thereference signal to the VCO clock signal.

Potential problem in PFD is the dead zone

which contains the nonlinearity in phase to

voltage transfer function. In fact, the main

criterion in designing PFD and charge pump is to

minimize the spurious frequency components

and the phase noise which is caused by the dead

zone in combination of PFD and charge pump or

the charge pump charging-discharging current

mismatch which is responsible for the increasingphase noise and spurious tone.

The normal and desired operating point for

PED is at zero phase. When the input signals of

PFD are nearly lock or phase error approaches

zero, the PFD output does not have a chance toreach full logic level before it is reset. This will

cause the up and down signal pulses not able to

make a complete transition due to finite rise and

fall times.When phase error falls in the dead zone, the

PFD fails to feedback the phase error informationto the VCO for correction. This will causes

output phase of VCO to drift without control and

thus increase the phase noise [2]. In this paper,

TSPC (true-single-phase-clock) technique is

utilized to achieved high speed operation and in

the same time overcome the dead zone problem.The true-single-phase-clock dynamic CMOS

circuit technique uses only one clock signal.Therefore, no clock skew exists except for clockdelay problems and higher clock frequency canbe reached. The TSPC CMOS technique fits indynamic circuits as well as static CMOS circuits[3],[4]Dynamic PFD using TSPC circuit is being

proposed to solve the speed limitation in

conventional PFD. By using the TSPC D typeflipflop, the operating frequency of the PFD canbe increased. The dynamic PFD only uses 20transistors as shown in Figure 2. This is a greatreduction which reduces the overall powerconsumption and increase the operating speed.Besides, dynamic PFD requires less area. Thecritical timing only consist 3 gate delays whichcontribute to higher operating speed and higherprecision-limits which results a smaller deadzone.

,.................................................... ......... ................

*m

.. .. .. .. .. .. .. .. ..

.,.

.,-*1SDSu a["

Figure 2: Critical delay path in dynamic PFD.

Voltage-controlled oscillator is a frequency-modulated oscillator whose instantaneous outputfrequency is directly proportional to its inputcontrol voltage. A ring oscillator can besmoothly integrated in a standard CMOS processwithout taking extra processing steps because itdoes not require any passive resonant elementcompare to CMOS LC-tank oscillator. In mostintegrated ring oscillators, fully differentialinverters are used to obtain better power-supplyinsensitivity.A voltage-controlled oscillator (VCO) is one of

the key elements in a phased-locked loop (PLL)and determnines the performance of a PLL. Ringoscillators are mainly used in mixed signal ICswhere baseband digital and analog RF share thesame die, a differential implementation is muchmore frequently utilized.Negative skew delay scheme is utilized to

overcome frequency limitation in conventionalring oscillator. In negative skewed delay scheme,negative delay element is inserted at one of thetwo transistor inputs (PMOS or NMOS) in theconventional CMOS inverter. Therefore the input

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ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

signal to the PMOS comes earlier than that of theNMOS.

In the skewed delay cell, the rising and fallingmechanisms of the output signals are differentcompare to the conventional inverter cell. Theskewed delay cell turns on the PMOSprematurely when the inverter output (out)having a low-to-high transition. Thiscompensates the performance of the PMOSwhich is slower than NMOS. When the outputtransits from high-to-low, the PMOS of theskewed delay cell turns off before the NMOSturn on which speeding up the transitioncompared to conventional inverter. Using thisscheme, higher oscillation frequency can beachieved compared to conventional inverter.Higher oscillation frequency or speed isachievable at the expenses of greater powerconsumption due to the time overlap when bothtransistors are on [5].

Figure 3 shows a differential delay cell.Differential structure is useful to reduce thepower-supply injected phase noise. Tail current

4..' - i ito- --t.

Figure 3: Two-input differential delay cell.

source normally implement using MOS transistoris avoided which reduce 1/f flicker noise.Basically, the delay cell is a simple differentialinverter. The differential inverter consists of Mland M3 pair and M2 and M4 pair as differentialinverter.A pair of PMOS load transistor M3 and M4

function as CMOS latch in the delay cell. Thisadded latch plays a major role in determining thedelay time in the oscillation thus controlling theoutput frequency. The cross-coupled NMOStransistor M5 and M6 control the maximum gatevoltage of the PMOS load transistor and limit thestrength of the CMOS latch.When VCONT iS low, M5 and M6 operate in

cutoff region and form a very high resistancepath between the gate of CMOS latch and vout+or vout- producing very low voltage at the gate

ofCMOS latch. The output driving current of thePMOS load increases. Depending on the currentflowing through Ml and M2, the current flowing

thste of~t>he lac to chang easily:. ThusW,the<I* *¢\

strength~~~~of pth lthecms wek Th vut

stage~~~~~~~~~~~~~~Mwhc consisYtcpitance Th deAy ell

d;.C:i.';'h"-rge to groun whe vn+ is h,..igand'schrg to powter supply.~ AMvol8+S@#tagwhe vinl ist}

swtching^>-.s.Sinceutheechrgn and.ditSchrgn

I -1i i-

Figure 4: Four input differential delay cell.

through M3 and M4 can vary easily which makethe state of the latch to change easily. Thus, thestrength of the latch becomes weak. The vout+and vout- are connected to the input of the nextstage which consist capacitance. The delay cellconsists of differential inverter, vout- willdischarge to ground when vinil is high andcharge to power supply voltage when vinl+ islow. These make the delay cell perform completeswitching. Since the charging and dischargingtime is quick, this causes only small delay time toinvert the signal from vinl+ or vinl-.When VCONT is high, the strength of the latch

becomes strong. This will cause the delay cell toresists voltage switching and thus delay timeincreases. Full-swing waveform can be generatedsince delay cell is basically a simple differentialinverter [6].To achieve a higher oscillation frequency,

negative skew delay scheme can be implementedeasily by adding 2 additional PMOS transistor inthe two-input differential delay cell as shown inFigure 4 to take the negative skewed signal.Ring oscillator with normal delay path has

wider tuning range but cannot achieve a higheroperation frequency. For ring oscillator withskewed delay path, a higher operation frequencyis achievable but in the expense of lower tuningrange. Therefore, a higher operation frequencyand wider tuning range can be achievedsimultaneously using both of the delay schemecalled dual-delay scheme.The negative skewed delay paths decrease

the unit delay time of the ring oscillatorbelow the single inverter delay time and thusincrease the operation frequency while thenormal delay path maintaining the tuning

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range. Using these fact, a differential inputand single-ended control voltage VCO orring oscillator can be implemented withdual-delay path using the 4-input differentialdelay cell.

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44,

Josl

4 4

'v Iw.

;,I~~4

t08 9 --1- t5> 9

,;4ys<t.Ni g v:s \-t*<;;\ >

Figure 5: Single-ended output charge-pump.

Charge pump is widely used in modem phase-locked loop for low-cost IC solution. It is thedominant block that determines the level of theunwanted FM modulation causing the referencespur due to mismatch. Generally, it can bedivided into single-ended and differential chargepump with 4 distinctive charge pumparchitecture which are conventional tri-state,current steering, differential input with single-ended output and fully differential charge pump.The function of charge pump and loop filter is

used to transforms the timing information whichis the up and down signals from the PFD toanalog quantity in low frequency control voltageto control the VCO.

Single-ended input single-ended output chargepump is being used. As shown in Figure 5, thereare five current mirrors consists of M2, M3, M5,

Figure 6: Second order loop filter.

M6, M7, M8, M9, MIO and Ml 1.When UP is HIGH and DN is LOW, M4 is

OFF, therefore more current from M9 flowthrough M5 and mirror to M6. Since Ml is ON,more current flow through M 1 which results lesscurrent flow through M2 and mirror to M3. Thiswill cause a net current flow into the loop filter

which charge-up the loop filter. The operation isreverse when DN is HIGH which result in a netcurrent flow from loop filter into M 1I thusdecrease the control voltage, VCONT.The transistor been adjusted such that Ml and

M4 will operate in triode region to avoids fullyon or off condition. Thus, it speeds up the circuitoperation. In order to reduce the contribution ofdead zone from charge pump, fully symmetriccharge pump architecture for the charge up andcharge down portion is used to reduce themismatch.A passive filter is chosen for implementation.

The loop filter is mainly a low-pass filter used toremove any noise and high-frequencycomponents from the output voltage of the phasedetector and charge pump thus giving an average(dc) voltage to control the VCO outputfrequency. To appropriately suppress the noise of

I s+ I

GLPF (S) = 1CISC2 S + RC2 + R (1)

the VCO, a second-order loop is required (Figure6). The capacitor implements an integrator whilethe resistor provides a compensation zero forPLL. By including an integrator in the PLL, thephase error between the VCO output and thereference is forced to be zero. Capacitor C2 isadded to reduce output ripple. Loop filter is usedto stabilize the PLL operation. The transferfunction GLPF(S) for the loop filter is given asbelow.

III. SIMULATION RESULT

A complete test case for dynamic PFDincluding the locked and unlocked condition issimulated and the phase characteristic ispresented as shown in Figure 7. The PFDcharacterization had been carried out by writingtest cases ranging from -540' (3rt) to 540° (3rc) ofphase error, 0, for 900MHz and l.lGHz input.No dead zone hazard is observed as shown inFigure 8.Figure 9 shows the VCO frequency

characterization. The VCO had been tuned andoptimized such that it will operate at 900MHzwhen VCONT=1.25V.To ensure the VCO will function properly, it is

recommended to operate the control voltage,VCONT between IV and 2.5V. From Figure 9,tuning range, frlnge is 600MHz.

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ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

-4 -3 -2 -1 0 1 2 3 4Phase Error, 0 [pi radJ

Figure 7: Phase characteristics of the dynamic PFDfor 900MHz and 1. I GHz input clock.

0.15

0.1

I-

.005

0.1

-0.1 s

-01 -0.05 0 0.05

Phase Error, 0 [pi rad]

2 PDKVCOC, (1)

TABLE I

VCO DESIGN PARAMETERSPARAMETERS VALUES

KvIoC 2.25 GRAD/VS

KPFO 12.7 gA/RADKO 251 MRAD/s

(05 63 MRADIs

COP I GRAD/S(VS 63 MRAD/S

Setting C = 0.7 to get an overdamped responseand assuming R=k5Q and substituting the KPFD

.;

..:: .X..

0.1

Figure 8: No sign of dead zone at zero phase error.

05 0 05 1 15 2

Cot4ol voIaue, Vcout

Figure 9: VCO tuning frequency by co

VCONT.

A buffer is added at VCO outpulsinusoidal signal to square wave sigrthe charge pump simulation resultpump current, Icp=824A is obtaincurrent flow through M6 or Ml I in= 40MHz is chosen where Kbandwidth. Damping ratio is given a

3.

Figure 10: PLL locking response using 900MHzas input reference clock frequency.

and Kvco as shown in Table I yieldsR=5kQ,3zJ C-=2.5pF,and C2=0. 16pF.....,.........

simulation, all the

blocks are finally integrated and simulated using900M1z square wave input as reference clock.Figure 10 shows the PLL locked after IOOns and

........... settles to 1.1 9V. The ripple after PLL beinglocked is measured as 48.63mVpp. VCO output

25 frequency is measured as 900MHz duringlocked. The ripple is calculated to be 4.09%. The

)ntrol voltage, overall transistor and power consumption neededfor this PLL is tabulated in TABLE I1. The PLLonly requires 67 transistors and consumed

t to convert 23.81mW only which occupied lesser siliconial. Based on area for chip fabrication. Besides, the total power

the charge consumption required is lesser too.ed (measureFigure 7). K TABLE II

is the loopTOTAL TRANSISTrOR AND POWER CONSUMPTION

Block Total Total Power

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I^wrN#NS

;v - A

...........

.......................

.................................................................

VPFD(900MHz)

1101"2 2 r---r- 1- -'---7E--- ..1

"::::...= .............=IiWIMI.W.V-,,I130=

V.pw-- --f- --

I., I i. -j--i-

400

435

ICSE2004 Proc. 2004, Kuala Lumpur, Malaysia

Transistor Consumption______ (mW)

PFD 20 1.19VCO 36 18.60Charge pump and 11 7.28loop filterPhase-locked 67 23.81loop ._

REFERENCES

[1] B. Razavi, Monolithic phase-locked loops and clockrecovery circuits: Theory and design. New York: IEEEPress, 1996.

[2] L. Dai and R. Harjani, Design of high-performanceCMOS voltage-controlled oscillators. Boston: KluwerAcademic Publishers, 2003.

[3] J. Yuan and C. Svensson, "High-speed CMOS circuittechnique," IEEE J. Solid-State Circuits, vol. 24, no. 1,pp. 62-70, February 1989.

[4] K. Lee, D-K. Jeong, Kyungki-do, "High-speed andhigh-precision phase locked loop," U. S. Patent 6 462624, Oct. 8, 2002.

[5] S.-J. Lee, B. Kim, and K. Lee, "A novel high-speedring oscillator for multiphase clock generation usingnegative skewed delay scheme," IEEE J. Solid-StateCircuits, vol. 32, no. 2, pp. 289-291, February 1997.

[61 C.H. Park, and B. Kim, "A low-noise 900MHz VCO in0.6 m CMOS," IEEE J. Solid-State Circuits, vol. 34,no. 5, 586-591, May 1999.

[71 D.H. Wolaver, Phase-locked loop circuit design. NewYork: Prentice Hall, 1991.

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