ICSE2010 Proc. 2010, Melaka, Malaysia

Enhanced Performance of Vertical Double Gate MOSFET (VDGM) With Oblique Rotating

Implantation (ORI) Method

Ismail Saad1,2*, Munawar A. Riyadi2, Zul Atfyi F. M. N.2,3, Afifah Maheran A. Hamid3, Razali Ismail2

1School of Engineering & IT, Universiti Malaysia Sabah, 88999, Kota Kinabalu, Sabah 2Computational Nanoelectronics (CONE) Research Group, Universiti Teknologi Malaysia, Skudai 81310, Malaysia

3Faculty of Electronic & Computer Engineering, Universiti Teknikal Malaysia Melaka, 75450 Ayer Keroh, Melaka, Malaysia *Email: ismail_s@ums.edu.my / ismail_saad03@yahoo.com

Abstract—An enhanced performance of vertical double gate MOSFET (VDGM) structure was revealed by adopting the oblique rotating ion implantation (ORI) method. The device structure was simulated based on TCAD tools and verified by good matching data with the published experimental results. With ORI method a symmetrical self-aligned source/drain regions over the silicon pillar and sharp vertical channel profile was observed. With Lg = 50nm, the VT is 0.96V in double gate and increased to 1.2V in single gate structure. The sub threshold swing, S = 81.9 mV/dec and S = 87.7 mV/dec were obtained for double and single gate devices respectively. Similarly, large IDsat = 370µA/µm was observed for double gate compared to single gate device. By scaling the Lg into 50nm, the VT remains almost the same when the Lg is larger than 80nm. However, it decreases rapidly when scaled down to 50nm. The leakage current increases rapidly when the Lg is scaled down to 100nm and beyond. However, the ratio of ION – IOFF is seen to be increases even with shorter Lg. These results indicates that ORI method is essential for overcoming various SCE as scaling the channel length down to nanometer regime.

I. INTRODUCTION

A channel on a side of an insulating pillar made of SiO2 in a vertical MOSFET is forecasted to be an attractive solution [1] for sustaining the scaling of CMOS technology into nanometre regime. There are mainly two ways to fabricate vertical MOSFETs. One way is to use the expensive epitaxial growth (e.g., MBE, RT-CVD, SEG) to define the short-channel length [2]-[5]. Recently, solid-phase epitaxy (SPE) was also used to fabricate vertical MOSFETs [6]. However, these approaches are not CMOS compatible. The other way is to etch silicon pillars and then diffuse the implanted dopants without tilt angle to obtain a short channel [7]. However, the minimum channel length that can be reached in this way is limited by the height of silicon pillar dry etch and the thickness of nitride fillets [8]. As a result, unacceptable high-threshold voltage, large leakage current, DIBL and GIDL is observed for 125nm devices. This limits the scaling of such devices into nanometre regime. To address these problems, an oblique rotating ion implantation (ORI) method was employed for making the self-aligned

symmetrical source regions near and over the edge of silicon pillar [9]. In this way, a sharp vertical channel profiles over the pillar will be obtained and this will improve the current drivability and the controllability of threshold voltage and subsequently to suppress the short channel effect (SCE) when scaling the device into nanometre regime [10]. In the following sections, the analysis of adopting ORI method for multiple gates structure and nano-scaling of VDGM were presented respectively.

II. DEVICE STRUCTURE AND PHYSICAL MODELS The proposed device structure is similar to vertical MOSFET with fillet-local-oxidation (FILOX) for parasitic capacitance reduction [11]. However, here the structure has been enhanced with symmetrical self-aligned source/drain region and sharp vertical channel profile over the silicon pillar. The method of oblique rotating ion implantation (ORI) is employed for revealing this unique feature of the device structure. Figure 1 shows the cross-section view of n-type VDGM fabricated by utilizing ORI method. In general, drift-diffusion models are known to underestimate the drive current in MOSFETs at deep submicron geometries [12]. Therefore, the absolute values of drive current in these simulations may not be accurate. However, for the purpose of comparison study based on identical models for both devices the analysis on current-voltage characteristics and secondary effects are to be captured well [13].

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ICSE2010 Proc. 2010, Melaka, Malaysia

Fig. 1. Cross section of vertical MOSFET with oblique rotating ion

implantation (ORI) method Since vertical MOSFET is non-planar device, the correlation between carrier mobility, carrier concentration, temperature and the electric field can be described as semi-empirical equation presented in Ref. [14]. In a low electric field, the carrier mobility is given by three components that are combined using Matthiessen’s rule given as

1111 srbACT (1)

µAC is the surface mobility limited by scattering with acoustic phonons given by

ET

CNEB

LAC

81

(2)

where B=4.75x107 cm/s, C=1.74x105, N is total doping concentration, E transverse field and TL is lattice temperature in Kelvin. µb is the mobility limited by scattering with optical intervalley phonons given by

21

68000

52

0 11300

As.

rA

.Lm

b /NCµ

/CNµ/Tµµµ

(3)

where o=52.2 cm2/(V.s), m=1417 cm2/(V.s), 1=43.4 cm2/(V.s), Cr=9.86x1016 cm-3, Cs=3.43x1020 cm-3 and NA is the total density of impurities. µsr, the surface roughness factor for electrons, is given by

2

Esr (4)

where =5.82x1014 cm2/(V.s). The mobility degradation due to present of electric field is given by the relation

21||0|| 11)( VSATNEE nonn (5)

where µn0 is the electrons low-electric-field mobility and E|| is the longitudinal electric field in the direction of current.

VSATN is the saturated drift velocity calculated from temperature-dependent model [15]. LTCVSATN exp1* (6)

where *=2.4x107 cm/s, C=0.8 and =600K. The carrier’s generation-recombination model is based on phonon transition occur in the presence of one level trap within the forbidden gap. The theory is described by Shockley-Read-Hall equation [16] assuming fixed carrier lifetime given by

ii

iSRH npxnnx

npnR

77

2

101101 (7)

where n and p is the electron and hole concentrations respectively, ni is the intrinsic equilibrium concentration and 1x10-7 second is the carrier lifetimes. An interface fixed oxide charge of 3x1010 C/m2 is assumed with the presence of n-type polysilicon gate.

III. DEVICE PROFILES AND CHARACTERIZATION

Figure 2 illustrates electron concentration profile along the vertical channel from source to drain region approximately 2 nm below the Si-SiO2 interface for both vertical MOSFETs fabricated with ORI and without ORI technique at VDS = 2V and VGS = 0 V. As depicted in Fig. 2, vertical MOSFET with ORI device has larger concentration of electrons inside the channel injected from the source as drain voltage increases compared to that without ORI method. This is mainly due to symmetrical self-aligned source/drain region over silicon pillar during tilted and rotated ion implantation process. Therefore, the off-state leakage current and DIBL effect can be reduced significantly. In addition, the self-aligned regions create a sharp vertical channel profile over the silicon pillar and reduce the channel length. As a result an improved drive-on current can be observed prominently. The combination of Gummel and Newton numerical methods was employed for a better initial guess in solving quantities for obtaining a convergence of the device structure. Figure 3 shows the comparison of vertical MOSFET transfer characteristics between single and double gate structure with Lg = 50nm, oxide thickness, tox= 3.0 nm, body doping, NA = 5.0x1018 cm-3 and at drain voltage, VDS = 1.5V. Based [18] method, the threshold voltage (VT) is extracted to be 0.96V in double gate and increase to 1.2V in single gate structure. This result confirms that better electrostatic channel control is achieved when the double gate structure is employed. Therefore making the VT variation is well under control as needed for circuit and system level design.

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ICSE2010 Proc. 2010, Melaka, Malaysia

0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18100

105

1010

1015

1020

1025

Distance along Channel (m)

ELE

CTR

ON

CO

NC

EN

TRA

TIO

N (c

m-3

)

with ORIwithout ORI

Nbody=5x1018cm-3, tOX=3nm VDS=2V, VGS=0V

Source DrainIncrease Lg

Silicon Pillar

Fig. 2. Electron concentration profile of vertical double gate MOSFET for both with ORI and without ORI method at VDS=2V and VGS=0V

However, as observed in Fig. 3, very little asymmetry can be dictated between single and double gate devices. The leakage current (IOFF) and the drive on current (ION) is shown to be higher in double gate compare to single gate. An IOFF = 2.74 x 10-14 A/m and ION= 1.8 x 10-4 A/m is measured for double gate vertical MOSFET. While for single gate device an IOFF = 1.74 x 10-14 A/m and ION= 0.8 x 10-4 A/m was observed. The sub-threshold swing S = 81.9 mV/dec and S = 87.7 mV/dec are obtained for double and single gate devices respectively. These results indicate that vertically defined channel with ORI technique was a potential candidate for scaling CMOS technology down to 50nm even if a single gate structure is used. Similarly, a large drain saturation current, IDsat = 370A/m was observed for double gate compared to single gate device with IDsat=170A/m as evidence in Fig. 4. This is due to an increase of channel width per transistor area in double gate and eventually increase the drive on-current defined as drain saturation current at VDS = VGS = 1.5V. The dependency of drain current to channel width in nanoscale transistor can be explicitly verified from developed models in [19].

0 0.5 1 1.5 2 2.5 310-16

10-14

10-12

10-10

10-8

10-6

10-4

10-2

GATE VOLTAGE, VGS(V)

DR

AIN

CU

RR

EN

T, I D

S (A/

m)

Double GateSingle Gate

Fig. 3. The comparison between single and double gate structure of vertical

MOSFET transfer characteristics with Lg=50nm, tox=3nm and VDS=1.5V

0 0.5 1 1.50

50

100

150

200

250

300

350

400

DRAIN VOLTAGE, VDS (V)

DR

AIN

CU

RR

EN

T, I D

S ( A

/ m

)

Double GateSingle Gate

Fig.4. The comparison between single and double gate structure of vertical MOSFET output characteristics with Lg=50nm, tox=3nm and VGS=1.5V

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ICSE2010 Proc. 2010, Melaka, Malaysia

IV. SCALING ANALYSIS The threshold voltage (VT) roll-off characteristics of VDGM with scaled channel length from 100nm down to 50nm are shown in Fig. 5. The threshold voltage remains almost the same when the channel length is larger than 80nm. However, it decreases rapidly when the channel length is scaled down to 50nm due to short-channel effects (SCE). In addition, the threshold voltage in the saturation region (VDS = 1.0V) is smaller than that in the linear region (VDS = 0.025V) because of the drain-induced barrier lowering (DIBL) effect. The DIBL effect can be explain as follows. When the drain voltage increases, a larger electric field is coupled to the back gate through the back oxide. Thus, the body potential is affected by the higher electric field and the back channel is turned on even though the gate voltage is still at zero or negative bias. This is the reason why the threshold voltage variation ( VT) and the leakage current become larger as the drain voltage increases. The shorter the channel length, the more the threshold voltage variation. For example, DIBL (defined as VT(Vds=0.025V) – VT(Vds=1.0V)) for the 100 and 50nm devices is 62 and 164 mV, respectively.

50 60 70 80 90 100

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

EFFECTIVE CHANNEL LENGTH (nm)

THER

SH

OLD

VO

LTA

GE

, VT (V

)

VDS=0.025V

VDS=1.5V

Fig. 5. The threshold voltage (VT) roll-off characteristics of VDGM with ORI method extracted at VDS = 0.025V and 1.5V

The ION – IOFF characteristics are summarized in Fig. 6. The leakage current IOFF is measured at VDS = 1.0V, VGS =0V and the ION is measured at VDS =1.0V and VGS – VT = 1V. An on-current of 588 A/m was obtained at the leakage current of 5.52 x 10-14 A/m for the 50-nm device. However this on-current is smaller compared to the reported value of 900 A/m in the ITRS roadmap (ITRS 2007) might due to non-silicidation of the source/drain contacts and thicker gate oxide used here. The leakage current increases rapidly due to the

short-channel effects when the channel length is scaled down to 100nm and beyond. However, the ratio of ION – IOFF is seen to be increases even with shorter channel length. These results indicates that ORI method applied to vertical MOSFET structure is essential for overcoming SCE and maintain good ratio of leakage and drive current as scaling the channel length down to nanometer regime.

300 350 400 450 500 550 60010

-16

10-15

10-14

10-13

ON CURRENT, ION (A/m)

LEA

KA

GE

CU

RR

ENT,

I OFF

(A

/ m

)

Leff=50nmLeff=80nm

Leff=90nmLeff=100nm

Fig. 6. The ION – IOFF characteristics of VDGM with ORI method for effective channel length Leff = 100nm down to 50nm

V. CONCLUSION

High performance vertical double gate MOSFET (VDGM) was demonstrated and characterized using both process and device simulations. The unique structure of vertical MOSFET was defined using oblique rotating ion implantation (ORI) during source/drain self-aligned process. It is found that using this method, a sharp vertical channel is achieved that will enhance the controllability of threshold voltage variation, current drivability and short channel effects (SCE).

ACKNOWLEDGEMENT

The authors would like to acknowledge the financial support from E-Science fund of MOSTI Malaysia. The author is thankful to the Universiti Teknologi Malaysia for providing excellent research environment in which to complete this work.

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