FPGA-Based Pulse-Width Modulation Control

For Single-Phase Multilevel Inverter

Wahidah Abd. Halim1 and Nasrudin Abd. Rahim

2

1Faculty of Electrical Engineering, Universiti Teknikal Malaysia Melaka (UTeM), Melaka, Malaysia.

2UMPEDAC Research Centre, University of Malaya, Kuala Lumpur, Malaysia.

wahidahhalim@utem.edu.my1, nasrudin@um.edu.my

2

Abstract— Presented is pulse-width modulation (PWM) for

single-phase five-level inverter via field-programmable gate

array (FPGA). The proposed inverter has conventional full-

bridge configuration and one bidirectional switch. The control

technique is digitally generated based on multicarrier PWM in

Altera DE2 board, which has many features that allow

implementation of the system design through Cyclone II FPGA

device. A sinusoidal reference signal and two triangular carrier

signals in phase and of the same frequency but different offset

voltages were used to generate the PWM signals for the inverter

switches. Besides Altera Quartus II software, Matlab/Simulink

software was used to simulate and verify the proposed circuit

before it was implemented in a prototype hardware. Simulation

and experiment results closely agreed.

Keywords – Pulse-width modulation (PWM), FPGA, multilevel

inverter.

I. INTRODUCTION

Multilevel inverters have been drawing huge interest since recent years, especially in high power and power quality applications. They are advantageous over traditional three-level ones; [1]-[3] near-sinusoidal output waveforms, smaller filter size, lower electro-magnetic interference (EMI), and lower total harmonic distortion (THD) are some of the characteristics that make it popular among researchers and industries.

A multilevel inverter’s output comprises several intermediate voltage levels stepped through. Fig. 1 shows a typical phase-output voltage for three-level and five-level inverters. Generally, there are three common topologies for multilevel inverters: neutral point clamped (NPC) or diode clamped, flying capacitor (FC) or capacitor clamped and cascaded H-bridge (CHB).

The most common modulation methods developed for multilevel inverters are multicarrier pulse-width modulation (PWM), selective harmonic elimination (SHE), and space-vector modulation (SVM). In multicarrier PWM, the carriers can be arranged as follows: phase shifted (PS), phase disposition (PD), phase opposition disposition (POD), or alternate phase opposition disposition (APOD) modulations [1]-[3].

Emergence of field-programmable gate array (FPGA) technology created opportunities for its digital implementation in industrial control system. FPGA technology offers shorter

design cycle, much faster computation speed, reduced cost, less-complex circuitry and convenient application in algorithm modification. FPGA-based digital controllers have been successfully used in applications such as PWM inverters [4], multilevel converters [5], power-factor correction [6], and electrical-machine control [7].

This paper presents a single-phase five-level inverter with PWM generator on Altera DE2 board. The output voltage of the proposed inverter can be represented in the following five levels: +Vdc, +½Vdc, zero, -½Vdc and -Vdc, where Vdc is the magnitude of the dc voltage source. Altera Quartus II software was used to design the PWM pattern in the form of Verilog hardware description language (HDL) and schematic design entry.

II. THE OPERATIONAL OF PROPOSED INVERTER

Fig. 2 shows the proposed inverter’s configuration with LC filter and load resistor [8], [9], modified from conventional full-bridge inverter via addition of an auxiliary bidirectional switch comprising four diodes and one switch S5 connected at dc-source centre. Half levels (positive and negative values) of the PWM output voltages were obtained with proper switching control of the auxiliary bidirectional switch.

The proposed inverter uses a sinusoidal wave as a reference signal (50 Hz) with two triangular carrier signals (20 kHz) to generate the PWM gating signals, as illustrated in Fig. 3 [8]. The carrier waves were in phase and had the same frequency but different offsets. The switching functions were produced by comparing the modulating (reference) signal with the upper and the lower carrier signals.

The work was supported by the University of Malaya via its Postgraduate Research Grant scheme.

Figure 1. Output voltage waveforms for (a) three-level and

(b) five-level inverters.

(a) (b)

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Table 1 lists the inverter’s switching states. Switches S1, S3, and S5 would be operated at carrier-signal frequency, S2 and S4 to be switched at 50 Hz fundamental frequency. Only two switches would be operated at any one time.

Modulation index Ma of the proposed five-level inverter is defined as [8],

C

Ma

A

AM

2 (1)

where AM is the peak value of the reference signal and AC is the carrier’s peak-to-peak value. Behavior of the proposed five-level inverter was obtained when the modulation index ranged

between more than 0.5 and less than or equal to 1 (0.5 Ma ≤1).

TABLE I. SWITCHING STATES AND OUTPUT VOLTAGE OF THE

PROPOSED INVERTER

S1 S2 S3 S4 S5 Vab

ON OFF OFF ON OFF +Vdc

OFF OFF OFF ON ON +½Vdc

OFF/ (ON)

OFF/ (ON)

ON/ (OFF)

ON/ (OFF)

OFF/ (OFF)

0

OFF ON OFF OFF ON -½Vdc

OFF ON ON OFF OFF -Vdc

III. PWM GENERATION VIA FPGA

Control algorithm of the proposed inverter was digitally implemented in an Altera DE2 board. The DE2 board has Cyclone II 2C35 FPGA device as the main feature consists of 33 216 logic elements (LEs), 483 840 total RAM bits, 35 embedded multipliers, 4 PLLs, and 475 user I/O pins. Other

features used on the DE2 board are a 50 MHz oscillator for clock source, one pushbutton switch for system reset and five toggle switches for the selection of modulation index values.

Fig. 4 presents the block diagram of a single-phase PWM generator developed in Altera Quartus II software. The Quartus II software is the most comprehensive environment available for an FPGA design. The implementation of PWM generator was done in Verilog HDL and schematic design entry.

Relationship between sampling frequency and carrier frequency is based on Nyquist sampling theorem [10], which states that sampling frequency fs must be at least twice the analog signal’s highest frequency component. Equation (2) defines the relationship between carrier frequency and sampling frequency,

cs ff 2 (2)

where fs is sampling frequency and fc is carrier frequency.

Carrier frequency for the PWM was set to 20 kHz, whereas controller sampling frequency fixed at 40 kHz met Nyquist theorem’s minimum requirement. The modulating and the carrier signals were sampled at 40 kHz frequency and stored in lookup tables (LUTs). A 50 MHz oscillator on the Altera DE2 board was used to clock the overall system, defined as the main system’s clock frequency fsys. The system clock was thus divided by k = 1250 to adjust with LUT data count,

s

sys

f

fk (3)

where fsys is the main system clock frequency and fs is the sampling frequency.

Figure 3. The carrier and the reference signals for the PWM

generation.

0.48 0.482 0.484 0.486 0.488 0.49 0.492 0.494 0.496 0.498 0.50

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Time

Figure 2. The five-level inverter equipped with LC filter and a resistive

load.

S5

D3

Vdc1

Vdc2

S1 S2

S3 S4

D1 D2

D4

C1

C2 Cf

Lf

VAB +

VO

-

IL

RL

System Clock

50MHz

Clock Divider

(÷1250)

Sinusoidal Wave Generator

180˚ reference

generator

90˚Data

(LUT/ROM)

Modulation Index

Comparator

1 & 2

Pulse Logic

Pulses

S1, S2, S3, S4, S5

Triangular Wave Generator

Carrier 1 (LUT) Carrier 2 (LUT)

Q1 Q2 Q3

Figure 4. Block diagram of the PWM generator.

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The modulator uses a 900 sine wave LUT and programmed

it in RAM. There are N = 200 data generated for 900 (quarter

cycle) of a sine waveform as expressed in (4). Thus, 400 points are represented for one complete half cycle of the sine waveform.

sin4 f

fN s (4)

where fs is 40 kHz sampling frequency and fsin the 50 Hz reference frequency.

The sine-wave data was then multiplied by the amplitude modulation index Ma to produce the modulating signal. For the upper and the lower triangle waveforms, two data of different magnitudes were stored in the LUT. The upper and the lower carrier signals were compared with the modulating signal to produce the PWM signal.

To prevent a short circuit across the input voltage source, dead-time Tdead was included in the gating signals of the switches at each inverter leg [8]. The dead-time (usually called delay time or blanking time) was relatively short. The magnitude of Tdead was set to 0.2 µs during switch on and switch off of the PWM, whose response to dead time is shown in Fig. 5.

Fig. 6 illustrates the PWM scheme generator designed in Altera Quartus II software. Three schematic blocks represent frequency divider, pulse generator, and dead-time modules. Fig. 7 shows the Verilog HDL frequency-divider-module design entry for construction of 40 kHz sampling frequency and dead-time.

Fig. 8 depicts the schematic diagram of the sine-wave, carrier waves, modulation index and pulse logic blocks in the pulse-generator module. Fig. 9 shows the register transfer level (RTL) graphic for the pulse-logic module designed for the PWM generator. The Quartus II software lets the designer view the RTL graphic of the design entry. This view most closely represents the system, designed in FPGA.

IV. SIMULATION AND EXPERIMENTAL RESULTS

The proposed inverter’s model was simulated on Matlab/Simulink to verify its operation. Its FPGA-based PWM generator was designed by using Verilog HDL and schematic design entry; simulation was realized in Quartus II software. The PWM pattern was designed for modulation index Ma= 0.7. Performance of the proposed inverter system with LC filter and load resistor was observed.

Tdead(on) Tdead(off)

Figure 5. PWM signal with dead-time.

PWM

PWM with dead-time

Frequency Divider

Pulse Generator

Dead-time

Figure 6. Top level design of the PWM generator.

(a)

Figure 7. Verilog HDL code for the frequency-divider module, for

(a) sampling frequency, (b) dead time.

(b)

always @(posedge clk or negedge rstbar) begin if (!rstbar) Counter <= 0; else if (Counter != 1250-1) Counter <= Counter + 1; else if (Counter == 1250-1) Counter <= 0; end always @(posedge clk or negedge rstbar) begin if (!rstbar) clock_40khz <= 1; else clock_40khz <= (Counter <= 625-1); end

always @(posedge clk or negedge rstbar) begin if (!rstbar) dead_time <= 0; else dead_time <= ((Counter >= 1+10*0) & (Counter <= 1+5-1+10*0)) | ((Counter >= 1+10*1) & (Counter <= 1+5-1+10*1)) | ((Counter >= 1+10*2) & (Counter <= 1+5-1+10*2)) | ((Counter >= 1+1250-10) & (Counter <= 1+1250-5-1)) ; end

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Figure 11. Simulation result for the dead-time designed on Quartus II.

Tdead(on) Tdead(off)

PWM

PWM with dead-time

Fig. 10 shows the simulation results of the PWM signals

from Quartus II and Matlab/Simulink. Fig. 11 depicts the

simulation result for the 0.2 µs dead time design. Fig. 12 gives

the experiment results for the PWM switching signals;

generated by the DE2 board, they agreed well with those

obtained from the Quartus II and Matlab/Simulink

simulations.

For simulation purposes, the dc bus voltage is set to 200 V.

The proposed inverter was implemented with LC filter where

Lf = 3 mH, Cf = 470 F and the resistive load is 100 . Fig. 13

shows the simulated waveforms of the output voltage before

and after filtering. Fig. 14 shows the output voltage and load

current waveforms.

The PWM switching pattern developed in the Altera DE2

board was tested in a prototype of the proposed inverter,

whose performance with LC filter and 0.2 s dead-time was

observed at modulation index Ma = 0.7. Fig. 15 depicts the

experiment result for the output voltage waveforms before and

after filtering. Fig. 16 shows the experiment result for output

voltage and load current waveforms. The simulation and

experiment results show that five-level output voltage VAB and

(a)

Figure 10. Simulation results for PWM switching patterns on (a) Quartus II, (b) Matlab/Simulink.

(b)

Pulse Logic

Comparators Carrier LUTs

Sine

LUT

Modulation

Index

Figure 8. Schematic diagram of the pulse generator block.

Figure 9. RTL design of pulse logic block in the PWM generator.

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sinusoidal filtered output voltage VO are identical. The load

current IL is nearly sinusoidal and in-phase with the filtered

output voltage VO. Fig. 17 shows the total harmonic distortion

(THD) of the filtered ac voltage, the THD being 2.41%.

0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.3-200

-150

-100

-50

0

50

100

150

200

Time

Figure 14. Simulation result for the output voltage and load

current waveforms.

VO

IL

S4

S5

S3

S2

S1

Figure 15. Experiment result for the output voltage waveforms,

before and after filtering. .

VO

VAB

Figure 12. Experiment results for the PWM patterns.

S4

S5

S3

S2

S1

Figure 13. Simulation result for the output voltage waveforms,

before and after filtering.

VO

VAB

Figure 16. Experiment result for the output voltage and load

current waveforms.

VO

IL

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V. CONCLUSION

PWM switching patterns were applied to the proposed

inverter switches to produce a five-level output voltage. Altera

FPGA enabled fast, flexible design and implementation.

Simulation and experiment results were satisfactory for pulse

generation, the five-level output voltage and the filtered output

voltage and current.

ACKNOWLEDGMENT

The authors thank University of Malaya for its provision of

the PS112/2009C grant from the Postgraduate Research Grant

scheme funding the research. The first author gratefully

acknowledges the scholarship sponsored by the Ministry of

Higher Education (MOHE) Malaysia and UTeM.

REFERENCES

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[2] J. Rodriguez, J. S. Lai and F. Z. Peng, “Multilevel inverters: A survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp.724-738, Aug. 2002.

[3] J. Rodriguez, L.G. Franquelo, S. Kouro, J.I. Leon, R.C. Portillo, M.A.M. Prats and M.A. Perez, “Multilevel converters : An enabling technology for high-power applications,” Proc of the IEEE, vol. 97, no. 11, pp. 1786-1817 , Nov. 2009.

[4] D. Puyal, L.A. Barragan, J. Acero, J. M. Burdio and I. Millan, “An FPGA-based digital modulator for full- or half-bridge inverter control” IEEE Trans. Power Electron., vol. 21, no. 5, pp. 1479-1483, Sept. 2006.

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[7] A. Myaing and V. Dinavahi, “FPGA-based real-time emulation of power electronic system with detailed representation of device characteristics”, IEEE Trans. Ind. Electron., vol. 58, no. 1, pp. 358-368, Jan. 2011.

[8] S. J. Park, F. S. Kang, M. H. Lee, and C. U. Kim, “A new single-phase five-level PWM inverter employing a deadbeat control scheme,” IEEE Trans.Power Electron., vol. 18, no. 18, pp. 831–843, May 2003.

[9] J. Selvaraj and N. A. Rahim, “Multilevel inverter for grid-connected PV system employing digital PI controller,” IEEE Trans. Ind. Electron., vol. 56, no. 1, pp.149-158, Jan 2009.

[10] T. L. Floyd, Digital Fundamentals, 10th Ed, New Jersey: Pearson Prentice Hall, 2009.

Figure 17. THD of the filtered ac voltage.

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