Multi-TAP Architecture for IP Core Testing andDebugging on Network-On-Chip

R. S. Rajagopal∗, M. Nadi S.†, C. Y. Ooi‡, M. N. Marsono§Faculty of Electrical Engineering,

Universiti Teknologi Malaysia,81310 Johor Bahru, Malaysia

Email: {selvakumar.rajagopal21∗, nadi.mahdieh†}@gmail.com, {ooichiayee‡, nadzir§}@fke.utm.my

Abstract—With the trend to deep-sub-micron (DSM) technol-ogy, the ability for post-fabrication testing has become a bigconcern for system-on-chip (SoC) designers. The testing problemof network-based SoCs is categorized into two major parts,intellectual property (IP) core testing and communication infras-tructure testing. This paper presents an IP testing platform usingmultiple-test-access-port (multi-TAP) for mesh-based network-on-chip (NoC). In our approach, the TAP ports of IPs areconnected together in a daisy chain. In addition, IEEE 1149.1standard (JTAG) is used to connect TAPs of IPs to the externaltester. The proposed platform provides comprehensive testing anddebugging for each individual IP without incurring dependencyto other IPs. The main advantage of the proposed platform is theability to bypass the IPs which are not involved in the processof testing. Hence, It reduces the required number of clock cyclesto send test vectors to the IP/IPs under test.

I. INTRODUCTION

As VLSI feature size shrinks, the density of transistors ina square meter unit increases. Hence, it is possible to placemany IP cores in a single chip to form a system-on-chip(SoC).The most important problem of the early on-chip systems isthe interconnections of intellectual properties (IPs). It seemsthat scalability problem of current interconnection has beensolved with network on chip(NoC) [1]–[4]. In this approach,switches are used to connect IPs instead of using shared buses.

There have been some growing concerns on the testabilityaspect of on-chip communication architecture [5]–[7]. Otherthan the challenges on testing the interconnect architecture,the ability to test IPs is also critical during platform validationand high volume manufacturing [8], [9]. Several design-for-testability (DFT) techniques have been proposed for NoCtesting [10], [11]. The testing of a massively parallel VLSIarchitecture has been studied in [11] based on boundary-scantechnique, which can cause unacceptable hardware overheador test cost. Li et al. [12] proposed a multiple data flit formatand a scan chain configuration method to maximize networkutilization. A design for test scheme was proposed by Tran etal. [5] to reduce test cost of an asynchronous NoC. Petersenand Oberg [6] proposed a simple scheme for switch and linktesting based on a built-in self-test (BIST) design. A channeltesting for bridging faults was proposed in [7]. Some DFTtechniques integrate test architectures into the SoC to easetesting procedure [5].

Some principles of the IEEE 1500 Standard [13] have beenused [14], [15] to wrap around the nodes and augment testa-bility feature to embedded cores. IEEE 1149.1 standard [16]which is known as JTAG is proposed for reusable core-baseddesigns. Typical cores nowadays have standard built-in TAP tofacilitate both on-chip testing and also design-for-debug (DFD)implementation and reuse. This development has triggeredadvancement of several multi-TAP architectures that makesuse of this embedded debug feature in IP to provide debugfacility for any number of IPs in a SoC by using the samenumber of external pins [8]. At the same time, promotingfuture IPs to be designed with this TAP feature, selectingthe correct architecture is considered a key point in reductionof testing and debugging efforts, decreasing test time, aswell as allowing effortless architectural reuse across differentplatforms and designs. Thereupon, an architecture with theability of observing internal nodes/signals after fabrication ishighly demanded.

In this paper, multi-TAP architecture is proposed as a testingplatform to directly test IPs on NoC. The proposed architecturedoes not pose inter-dependency between IP cores. Since IEEE1149.1-based compatible built-in debug port exists in most ofthe newly designed IPs, it is chosen for the communicationbetween IP cores and external tester. It allows the tester toread IPs’ functional status, change the configuration on-the-fly, manage the power and execute special instruction, debug,and update IPs’ internal memory with new patch. The bypassinstruction is added to jump over the IPs which are notinvolved in testing to reduce required time of transmission thetest vectors to the IP under test. From our analyses, between2 and 4 times test time performance gain is obtain for 10×10mesh size.

This paper is organized as follows. Section II discusses theproposed multi-TAP architecture for IP testing. The perfor-mance of proposed method is evaluated in Section III. Finally,conclusion and future works are in Section IV.

II. MULTI-TAP ARCHITECTURE FOR NOC

In the proposed testing methodology, JTAG is used as astandard TAP for communication between external tester andNoC. Test registers and test configuration registers reside inDFT Master block to enable certain test modes, and send testsignals to the corresponding unit. As depicted in Fig. 1, the

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required JTAG pins for TAP specification are test-mode-select(TMS), test-data-in (TDI), test-clock (TCK), and test-data-out(TDO) which are used to access the JTAG controller.

Fig. 1. JTAG interface in NoC-based SoC for design testability

In this testing methodology, each integrated IP in the NoCenvironment is assumed to have a TAP-based debug port. Itallows the IP to be accessed from the same JTAG interface.The structure of a node is shown in Fig. 2. It consists of arouter and an IP. The TAP port is directly connected to the IP.

Fig. 2. Node structure in MultiTAP architecture

The TAPs of IPs are stitched together to form a daisy chainwith DFT controller (DFT controller in Fig. 3 and DFT masterin Fig. 1 are same). The number of required test pins in thisarchitecture does not change according to the number of TAPsdue to the daisy chain formation. The daisy chain architectureis illustrated in Fig. 3.

A special characteristic of the proposed architecture is theability for enabling one or more TAPs at any desired time and

Fig. 3. Multi-TAP architecture: Daisy chain of IPs’ TAPs with DFT controllerand their connection with JTAG pins

bypassing the other TAPs in the chain. It is done regardless ofthe physical location of the IP in the NoC. Enabling TAPs istaken care by the stitching logic. The stitching logic consists ofconfiguration registers in the DFT controller. Fig. 4 illustratesa simple implementation of TDI stitching logic for IP3. Inthe case where only the TAP of IP1 is enabled, the ip tap tdisignal from the master TAP will be the data input of IP1 TAP.When the TAP is not enabled, the data input is assigned to 0to ensure that the instruction register (IR) of TAP is loadedwith a value of all zeros during the instruction-register-shiftstate (SHIFT-IR). Since TCK and TMS are shared among allTAPs, an instruction of all zeros is required to keep a TAPidle when it is not enabled and should be bypassed from thechain.

Fig. 4. Stitching logic for a sample IP’s TDI input

The advantages of the proposed multi-TAP architecture areas follows:

1) Simultaneous multiple IP testing: It allows any numberof IPs to be tested simultaneously. A common test can beexecuted instantly by enabling all TAPs simultaneously.

2) Selected IP testing: A desired IP can be tested by en-abling its TAP enable signal in DFT controller. Then, only

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one IP will be stitched in the TAP network. This allowsone-to-one communication between the DFT controllerand the TAP of the selected IP for testing.

3) Bypassing ability:The bypassing ability allows bypass-ing the IPs which are not intended for testing from thechain. It causes the reduction of the required time of shiftdata from the disabled TAPs.

4) JTAG compliance: This architecture is compliant withstandard JTAG tool. Thus, there is no need to design newsoftware for testing and debugging.

5) Reducing test pin overhead: It uses only one set ofJTAG standard pins to establish communication amongthe external tester and the internal IPs. Therefore, thenumber of JTAG pins is fixed even with increasingnumber of IPs and TAPs in the design.

6) Inter-TAP switching: This architecture allows the testerto set a test mode in one IP, and switch to another IP toset different test mode while waiting for the first IP tocomplete the task.

7) Independent IP and NoC testing: IPs can be testedindependently from the network infrastructure. Hence,both IPs and NoC can be tested independently and alsosimultaneously.

8) Other abilities: Having a debug port for each IP in theNoC design allows silicon validators to access internalconfiguration, status, debug and other test related registersof IPs. Changing device configuration, power manage-ment and special instruction execution are made possibleby this architecture. Microcontroller-specific instructionlike halt and set breakpoint can also be executed. IPtesting coverage is enormously improved due to the directaccessibility.

III. PERFORMANCE EVALUATION OF MULTI-TAP TESTINGMETHOD

In the proposed platform, each TAP of IP has an 8-bitinstruction register (IR) and a 32-bit data register (DR). Inorder to complete a single write operation, the external JTAGtool sends 40 bits of instruction and data serially in theseregisters. Sending each bit takes one TCK clock cycle. Hence,it takes 40 clock cycles to shift in data and instruction to anenabled TAP. It needs additional 8 clock cycles to traversefrom the TAP state machine to instruction-scan (IR-Scan) todata-scan (DR-SCAN) before it can complete the instructionand data write. Hence, It requires 48 clock cycles in totalfor a successful register read or write when only one TAPis enabled. An 8-bit instruction and a 32-bit data have to beshifted serially to each TAP for each executing instruction.This is different when inactive TAPs are put in bypass mode.An 8-bit instruction data still needs to be serially shifted into each inactive TAP to indicate a bypass condition. However,inactive TAP does not require 32-bit data but only 1-bit forbypass register, which is mandatory when TAP is in bypasscondition according to the TAP specification.

Clearly, as more TAPs are enabled in the daisy-chain ofTAPs, the required time for execution an instruction for all

TABLE ITOTAL TEST TIME TO COMPLETE A READ OR WRITE INSTRUCTION FOR

DIFFERENT TAP CONFIGURATIONS

Index of IP undertest

Tb(cycles) Tn (cycles)

1 48 484 75 1689 120 36816 183 64825 264 100836 363 144849 480 196864 615 256881 768 3248100 939 4008121 1128 4848

TAPs increases, considering the length of instruction and datathat need to be shifted in serially to all enabled TAPs. Insuch situation, TAPs that are enabled but inactive should beput in bypass mode. Therefore, no data need to be shiftedinto TAPs except a single bypass bit. Hence, the number ofrequired clock cycles is reduced to shift the data in for theentire enabled TAPs. The instruction length that needs to beshifted in, does not reduce even when more TAPs are enabled.This is because the bypass condition can only be fulfilled byshifting in appropriate instruction during instruction-shift(IR-SHIFT) state for all TAPs.

The number of required cycles to send a test vector to the ithIP in the chain using bypass mode(Tbi) and also non-bypass(Tni) are given by,

Tbi = 40 + 8i+ (i− 1) (1)

Tni = 40i+ 8 (2)

where i is the index of the IP under test.The required time toexecute instruction simultaneously increases according to thenumber of the enabled TAPs in the stitched network.

The required number of clock cycles to test an IP in bypass(Tb) and non-bypass (Tn) mode are demonstrated in Table I.The effect of increasing the number of IPs on required cyclesfor testing is also shown in Figure 5. It can be concludedthat testing an IP using bypass configuration always givesthe maximum performance, specially for the bigger NoCsand/or for the last IPs in the chain. Also, It can be seenthat by increasing the number of IPs in a chip the proposedmechanism to bypass IPs in the chain greatly improves thetesting performance compared to the non-bypass mode. Thetest time improvement factor is approximately between 2 and4 for 100 cores on an NoC.

IV. CONCLUSION

Early A multi-TAP architecture for testing embedded IPsof a NoC-based SoC was proposed in this paper. The keyadvantage of the multi TAP architecture is the compatibilitywith the IEEE 1149.1 or JTAG standard to facilitate SoCtesting and debugging on board by providing access to internalconfiguration registers, enabling test modes, controlling device

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Fig. 5. Test time analysis for an IP in bypass and non-bypass TAPconfiguration

behaviour, read test results and improve observability to allnodes after fabrication. Also, the ability of enabling each TAPof IPs independently from other TAPs is highly suitable totest and debug each IP on demand at a given time as well asto improve performance of testing for each IP. The test timeimprovement factor is shown to be approximately between 2and 4 for 100 cores on an NoC.

ACKNOWLEDGEMENT

This work was supported the Ministry of Science, Technol-ogy, and Innovation of Malaysia ScienceFund Grant 01-01-06-SF0797, UTM Vote No 79409.

REFERENCES

[1] W. J. Dally and B. Towles, “Route packets, not wires: on-chip inter-connection networks,” in Proc. Design Automation Conf, pp. 684–689,2001.

[2] L. Benini and G. De Micheli, “Networks on chips: a new soc paradigm,”Computer, vol. 35, no. 1, pp. 70–78, 2002.

[3] M. H. Ghadiry, M. Nadi, M. T. Manzuri-Shalmani, and D. Rahmati,“Effect of number of faults on noc power and performance,” in Proc.Int Parallel and Distributed Systems Conf, vol. 2, pp. 1–9, 2007.

[4] M. H. Ghadiry, M. Nadi, and D. Rahmati, “New approach to calculateenergy on noc,” in Proc. Int. Conf. Computer and CommunicationEngineering ICCCE 2008, pp. 1098–1104, 2008.

[5] X. T. Tran, Y. Thonnart, J. Durupt, V. Beroulle, and C. Robach, “Design-for-test approach of an asynchronous network-on-chip architecture andits associated test pattern generation and application,” IET Computers& Digital Techniques, vol. 3, no. 5, pp. 487–500, 2009.

[6] K. Petersen and K. Oberg, “Toward a scalable test methodology for 2d-mesh network-on-chips,” in Proc. Design, Automation & Test in EuropeConf. & Exhibition DATE ’07, pp. 1–6, 2007.

[7] E. Cota, F. L. Kastensmidt, M. Cassel, M. Herve, P. Almeida,P. Meirelles, A. Amory, and M. Lubaszewski, “A high-fault-coverageapproach for the test of data, control and handshake interconnects inmesh networks-on-chip,” vol. 57, no. 9, pp. 1202–1215, 2008.

[8] A. Margulis and D. Akselrod, “Multi-tap connection architectures forapplication specific integrated circuits,” in Proc. Canadian Conf. Elec-trical and Computer Engineering CCECE 2008, pp. 001635–001640,2008.

[9] P. P. Pande, C. Grecu, A. Ivanov, R. Saleh, and G. De Micheli, “Design,synthesis, and test of networks on chips,” IEEE Design & Test ofComputers, vol. 22, no. 5, pp. 404–413, 2005.

[10] D. Xiang and Y. Zhang, “Cost-effective power-aware core testing innocs based on a new unicast-based multicast scheme,” vol. 30, no. 1,pp. 135–147, 2011.

[11] C. Aktouf, C. Robach, and A. Marinescu, “A routing testing of avlsi massively parallel machine based on ieee 1149.1,” 1995. TestConference, 1995. Proceedings., International.

[12] M. Li, W.-B. Jone, and Q.-A. Zeng, “An efficient wrapper scan chainconfiguration method for network-on-chip testing,” in Proc. IEEE Com-puter Society Annual Symp. Emerging VLSI Technologies and Architec-tures, vol. 00, 2006.

[13] “IEEE std 1500 enables core-based SoC test development,” 2009. Design& Test of Computers, IEEE.

[14] B.-G. Ahn, J.-M. Jung, and J.-W. Chong, “Power-aware test frameworkfor network-on-chip,” in Proc. Third Int. Conf. Systems ICONS 08,pp. 103–107, 2008.

[15] A. M. Amory, E. Briao, E. Cota, M. Lubaszewski, and F. G. Moraes, “Ascalable test strategy for network-on-chip routers,” in Proc. IEEE Int.Test Conf ITC 2005, 2005.

[16] “IEEE standard test access port and boundary-scan architecture,” 2001.IEEE Std 1149.1-2001.

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