A HIGH SPEED TRISTATE BUFFER

Nurul Hidayah Binti Hairuddin

Bachelor of Engineering with Honours (Electronics and Computer Engineering)

2006

A mGH SPEED TRISTATE BUFFER

NURUL HIDAYAH DINTI HAIRUDDIN

This project is submitted in partial fulfillment of the requirements for the degree of Bachelor of Engineering with Honors

(Electronics & Computer Engineering)

Faculty of Engineering UNIVERSITI MALAYSIA SARA W AI<

2006

UNIVERSITI MALAYSIA SARA W AI(

R13a

BORANG PENGESAHAN STATUS TESIS

Judul: A lUGH SPEED TRISTATE BUFFER

SESI PENGAJIAN: 2/2005/2006

Saya NURUL HlDAYAH BINTI HAIRUDDlN (HURUF BESAR)

mengaku membenarkan tesis ... ini disimpan di Pusat Khidmat Maklumat Akademik, Universiti Malaysia Sarawak dengan syarat-syarat kegunaan seperti berikut:

I. Tesis adalah hak milik Universiti Malaysia Sarawak. 2. Pusat Khidmat Maklumat Akademik, Universiti Malaysia Sarawak dibenarkan membuat salinan untuk

tujuan pengajian sahaja. 3. Membuat pendigitan untuk membangunkan Pangkalan Data Kandungan Tempatan. 4. Pusat Khidmat Maklumat Akademik, Universiti Malaysia Sarawak dibenarkan membuat salinan tesis ini

sebagai bahan pertukaran antara institusi pengajian tinggi. 5. ... ... Sila tandakan ( ~ ) di kotak yang berkenaan

D I SULIT (Mengandungi maklumat yang berdrujah kese1amatan atau kepentingan Malaysia seperti yang termaktub di dalam AKT A RAHSIA RASMI 1972).

D I TERHAD (Mengandungi maklumat TERHAD yang telah ditentukan oleh organisasil badan di mana penyelidikan dijalankan).

[[] TlDAK TERHAD

~"'Ol'h

(TAWATANGAN PENULIS) (TANDATANGAN PENYELIA)

Alamat tetap: 2, PSN WIRA JAY A BARA T

21, TMN AMPANG, 31350 IPOH, PERAK. PUAN ROHANA BT SAP A WI Nama Penyelia

Tarikh: 7 APRIL 2006 Tarikh 7 APRIL 2006

CATATAN * Tesis dimaksudkan sebagai tesis bagi Ijazah Doktor Falsafah, Saljana dan Saljana Muda.

** Jika tesis ini SULIT atau TERHAD, sila lampirkan surat daripada pihak berkuasalorganisasi berkenaan dengan menyatakan sekali sebab dan tempoh tesis ini perlu dikelaskan sebagai SULIT dan TERHAD.

Laporan Projek Tahun Akhir berikut:

Tajuk: A High Speed Tristate Buffer

Nama penulis: Nurul Hidayah Binti Hairuddin

Matrik: 7000

telah dibaca dan disahkan oleh:

7 April 2006

Tarikh Puan Rohana Bt Sapawi

Penyelia

Dedicated to my beloved parent, brothers, lecturers andfriends. I love you so much ...

ACKNOWLEDGMENT

Bismillahirrahmanirrahhim ...

"In the name ofAllah most gracious and most merciful"

First and foremost, I would like to dedicate this project to my parent and family

members for their supports, encouragements and loves during the period of study.

A deepest gratitude must be extended to my supervisor, Pn Rohana bt Sapawi for

her unwavering support and guidance to the successful of this project.

I also would like to take this opportunity to express my sincerest appreciation

to Mr Ng Liang Yew and Mr Norhuzaimin lulai for their concern and advices. To Pn

Siti Kudnie bt Sahari as my second supervisor and to all lecturers in electronic

department, without you, I will not be able to know about engineering and electronics.

A special thanks to my colleagues and friends for their cooperation and

encouragement. Last but not 1 east , I am deeply grateful to those who were involved

directly and indirectly throughout the process of completing the project. Thank you ..

ABSTRAK

Projek ini memaparkan rekaan litar penampan CMOS dengan kelajuan

tinggi yang berkeupayaan untuk memacu kapasitan yang lebih besar berbanding

litar penampan CMOS biasa. Teknik yang digunakan dalam merekacipta litar ini

adalah berdasarkan litar "feedback" yang dapat mencapai ayunan penuh dari

pembekal voltan ke pembumian. Dalam projek yang dijalankan ini juga

dimasukkan keputusan hasil simulasi daripada litar yang dicadangkan berkenaan

masa kelambatan, masa naik, masa turun dan juga arus asas semasa "enable"

dengan menggunakan program Pspice. Selain berkelajuan lebih tinggi, penampan

ini memberi sumbangan dalam penggunaan pembekal voltan yang optimum.

ABSTRACT

This project presents a high speed CMOS tristate buffer design circuit which

has the capability to drive larger capacitive load compared to the conventional

CMOS tristate buffer. The technique used is based on the feedback circuit to

achieve a full swing operation from supply voltage to ground. In this project also

included the simulative results of propagation delay, rise time, fall time and base

current during enable by using Pspice. Besides having higher speed, the proposed

tristate buffer contributed in optimum power supply consumption.

TABLE OF CONTENTS

Page

Abstrak iii

Abstract iv

Table of Contents v

List of Figures viii

List of Tables x

List of Abbreviation xi

CHAPTER 1: INTRODUCTION 1

1.1 Introduction 1

1.2 Principle Objectives 2

1.3 Chapter Overview 2

CHAPTER 2: LITERATURE REVIEW 4

2.1 Complementary-Metal-Oxide Semiconductor (CMOS) 4

2.2 CMOS Inverter 5

2.2.1 Propagation Delay 7

2.2.2 Transition, Rise and Fall Time of CMOS Inverter 8

2.3 Pull-up Network (PUN) and Pull-down Network (PDN) 11

2.4 Short Circuit Current 14

2.5 Power Delay Product (PDP) 17

2.6 Energy Delay Product (EDP) 18

2.7 Tristate Buffer 19

2.7.1 CMOS Tristate Buffer 22

2.7.2 CMOS Feedback Tristate Buffer 23

CHAYfER3: METHODOLOGY 24

3.1 Introduction 24

3.2 Design Flow 25

3.3 Conventional CMOS Tristate Buffer Circuit 27

3.3.1 Circuit Description 28

3.4 Proposed CMOS Tristate Buffer Circuit 29

3.4.1 Circuit Description 30

3.5 The Width!Length (W/L) Values 31

CHAPTER 4: RESULT AND DISCUSSION 33

4.1 Introduction 33

4.2 During Pull-down (En = 1, Vin = High to Low) 34

4.2.1 Conventional Circuit Output Voltage 35

4.2.2 Proposed Circuit Output Voltage 35

4.2.3 Analysis 36

4.3 During PuU-up (En = 1, Vin = Low to High) 37

4.3.1 Conventional Circuit Output Voltage 38

4.3.2 Proposed Circuit Output Voltage 38

4.3.3 Analysis 39

4.4 Rise Time 40

4.4.1 Analysis 40

r I

4.5

4.6

4.7

4.8

4.9

Fall Time

4.5.1 Analysis

Short Circuit Current

4.6.1 Analysis

Power Delay Product

Energy Delay Product

Discussion

CIlAPI'ER 5: CONCLUSION AND

RECOMMENDATIONS

5.1 Conclusion

5.2 Recommendation

5.3 Problem Encountered

[,

REFERENCES

APPENDIXES

APPENDIX A: MODEL FOR CMOS DEVICES

APPENDIX B: MODEL PARAMETER FOR PSPICE

41

41

42

42

43

44

46

52

52

53

53

54

56

57

LIST OF FIGURES

FIGURE TITLE PAGE

2.1 Transistor symbols 6

2.2(a) CMOS inverter uses one NMOS and one PMOS transistor. 7

2.2(b) A simplified model of the inverter for a high input level. The output is forced to zero through the on-resistance of the NMOS transistor. 7

2.1 (c) Simplified model of the inverter for a low input level. The output is pulled to V DO through the on-resistance of the PMOS transistor. 7

2.3 Propagation delay 8

2.4 High-to-Iow output transition in a CMOS inverter 9

2.5 Low-to-high output transition in a CMOS inverter 10

2.6 Complementary logic gate as a combination of a PUN (pull-up network) and a PDN (pull-down network) 12

2.7 Simple examples illustrates why an NMOS should be used as a pull-down, and a PMOS should be used as a pull-up device

2.8 Impact of load capacitance on short circuit current 14

2.9 CMOS inverter short circuit current through NMOS transistor as a function of the load capacitance 15

2.10 Tristate buffer switch model 19

2.11 The symbol and truth table of tristate buffer (a) enable (b) inverted enable 20

2.12 Two possible implementations ofan enable tristate buffer (a) and

(b) En = 1 enables the buffer. 21

2.13 A CMOS feedback tristate buffer circuit 22

3.1 Tristate Buffer Process Flow 24

3.2 Conventional CMOS Tristate Buffer Circuit 26

3.3 Proposed CMOS Tristate Buffer Circuit 28

4.1 Conventional and proposed design during pull down 33

4.2 Conventional and proposed design during pull up 36

4.3 Conventional and proposed design during rise time 39

4.4 Conventional and proposed design during fall time 40

4.5 Tristate buffer short circuit current through NMOS transistor. 41

4.6 Graph of the propagation delays versus capacitive load 47

4.7 Graph of the propagation delays versus supply voltage 47

4.8 Graph of the Energy Delay Product versus supply voltage 48

4.9 Graph of the Energy Delay Product versus propagation delays 48

LIST OF TABLES

TABLE TITLE PAGE

4.1 Summarized calculations ofconventional design 45

4.2 Summarized calculations ofconventional design 46

,.r

C

CL

CMOS

EDP

fmax

GND

IC

Ipeu

J

PUN

PDN

PDP

Pay

BS

Voo

LIST OF ABBREVIATION

Capacitance

Capacitive load

Complementary Metal-Oxide Semiconductor

Energy delay product

Maximum frequency

Ground

Integrated Circuit

Peak current

joules

Pull-up network

Pull-down network

Power delay product

Average power

On resistance for NMOS transistor

On resistance for PMOS transistor

Time

Fall time

Average propagation delay

High to low propagation delay

Low to high propagation delay

Rise time

Source bulk voltage for NMOS transistor

Drain to drain voltage

f

VH

Yin

VLSI

Vo

VSB

Vso

Vss

VT

Vro

VTN

VlP

WIL

Z

Voltage High

Input voltage

Very Large Scale Integrated

Output voltage

Source bulk voltage for PMOS transistor

Source to gate voltage

Source to source voltage

Threshold voltage

Threshold voltage at zero bias

Threshold voltage for NMOS

Threshold voltage for NMOS

Width / length

High impedance

CHAPTER!

INTRODUCTION

1.1 Introduction

The massively used of tristate buffer in digital Very Large Scale

Integrated (VLSI) systems including microprocessor and memory has

required it to work in higher speed. This is the consequence of the thirst of

technology for its rapid growth.

For this reason, a tristate buffer of Complementary Metal-Oxide

Semiconductor (CMOS) technology will be designed for a higher speed. It

is an important part inside the circuit which will cause to the whole digital

system operation to work in a better condition or not due to its appearance.

Most of the electronic circuits especially in the computers required this

tristate buffer since it is connected to the bus. When other device is sending

on the bus, all other sending devices should be disconnected. This can be

achieved by setting the output buffers of those devices in high impedance

state that effective disconnect the gate from output wire [1]. This is an

advantage of tristate buffer over a nonnal buffer for its enable input to

control the incoming signals.

In this project, a high speed performance of tristate buffer will be

designed using PSpice tool. For the requirement of tomorrow's technology,

this tristate buffer will also be designed to drive higher capacitive loads.

1.2 Principle Objectives

In order to gain a good result, every project should have specific

objectives which must be achieved at the end of the project. This is one way

ofencouragement for a better work out. The objectives of this project are:

1. To design a high speed tristate buffer based on CMOS technology.

11. To design tristate buffer that can drive larger capacitive load which

is suitable for driving a data bus.

iii. To develop and simulate circuits using PSpice.

1.3 Chapter Overview

The report documentation of this project is organized into five

chapters. The first chapter generally introduces the tristate buffer. It also

explains in brief the objectives and overview of the project.

Chapter 2 will present a brief discussion due to the performance and

behavior of the CMOS circuit. The characteristics and parameters of the

device will also be discussed in this chapter. This infonnation will guide to

design and contribute to a better perfonnance circuit than the current design.

In Chapter 3 will explain the methodology to design the proposed

CMOS tristate buffer with the technique which has been used. The

description of the conventional design is explained in this chapter so the

comparison of the circuits can be observed.

The simulation derived from the design in Chapter 3 will be

discussed in Chapter 4. The discussion is about the development of the

program simulation using simulation tool and also based on the results and

observations.

Chapter 5 will conclude the overall project which has been done

throughout two semesters. Recommendations for better work in the future

will be suggested due to discussions from the previous chapter .

..,

CHAPTER 2

LITERATURE REVIEW

2.1 Complementary Metal-Oxide-Semiconductor (CMOS)

CMOS technology is by a large margin the most dominant of all the

IC technologies available for digital-circuit design. CMOS has replaced

NMOS, which was employed in the early days of VLSI in the 1970s. There

are a number of reasons for this development, the most important of which

is the. much lower power dissipation of CMOS circuits. CMOS has also

replaced bipolar as the technology of choice in digital-system design and

has made possible levels of integration (or circuit packing densities) and a

range of applications that would never have been possible with bipolar

technology. Furthermore, CMOS continues to. advance, whereas there

appear to be few innovations at the present time in bipolar digital circuits

[2].

Some of the reasons for CMOS displacing bipolar technology in

digital applications are because CMOS logic circuits dissipate much less

power than bipolar logic circuits and thus one can pack more CMOS circuits

on a chip than is possible with bipolar circuits [2].

The feature size (that is minimum channel length) of the MOS

transistor has decreased dramatically over the years. This penn its very tight

circuit packing and correspondingly very high levels of integration [2].

All of these advantages had created an idea to build a tristate buffer

using the CMOS. The next section will review the objectives of designing

the tristate buffer and the overview after choosing the type of CMOS

devices.

2.2 CMOS Inverter

In designing the tristate buffer, the CMOS device is chose as

mentioned earlier in the previous chapter. But before the circuit is designed,

the characteristics of the device should be investigated in order to build a

good or even better circuit. In this chapter, the characteristics and

performance of CMOS which related to tristate buffer will be covered.

Before proceed with other explanation, the symbols of transistor used is

acknowledged in Figure 2.1.

(a) PMOS (b) NMOS

Figure 2.1: Transistor symbols

Inverter is the basic device of constructing CMOS gate, including

the tristate buffer. Figure 2.2 shows the static CMOS inverter. The source of

the PMOS transistor is connected to Voo, the source of the NMOS transistor

is connected to Vss (0 V), and the drain terminals of the two MOSFETs are

connected together to fonn the output node. The substrates of both NMOS

and PMOS transistors are connected to their respective sources, and so body

effect is eliminated in both devices [3], where VSB= 0 = VBS [4].

Simplified models for the CMOS inverter operation appear in Figure

2.2(a) and Figure 2.2(b). The input signal controls the state of the two

switches that effectively work as a single-pole double throw switch. In

Figure 2.2(b), the input is at a low input level (Vin = 0), and the output is

connected to Voo through the on-resistance of the PMOS transistor. In

Figure 2.2(c), the input is at high input level (Vin = Voo), and the output is

connected to ground through the on-resistance of the NMOS transistor.

Voo

(a)

Figure 2.2: (a) CMOS inverter uses one NMOS and one PMOS transistor.

(b) A simplified model of the inverter for a high input level. The output is

forced to zero through the on-resistance of the NMOS transistor. (c)

Simplified model of the inverter for a low input level. The output is pulled

to VDD through the on-resistance of the PMOS transistor [3].

2.2.1 Propagation Delay

Delay is one of the most important properties of a logic area. The

majority of the chip designs are limited more by speed than by area. In this

case, delays are estimated to gain high speed tristate buffer design. Delay is

considered as the time it takes for a gate output to arrive at 50% of its final

value as be shown in Figure 2.3 below.

g

V/n

Input waveform

output waveform

Figure 2.3: Propagation delay [4]

Propagation delay is caused by output capacitance; the input rise

time, tr and fall time, tr, series of transistors, the supply voltage which higher

Voo causes delay, and temperature (the higher temperature causes more

delay).

2.2.2 Transition, Rise and Fall Time of CMOS Inverter

Figure 2.4 illustrates the high-to-Iow output transition in a CMOS

inverter. Figure (a), for t < 0, the NMOS transistor is off and the PMOS

transistor is on, forcing the output to the high state with Vo = VH = VDO.

Figure (b), at t = 0, the input abruptly changes from 0 V to 5 V, and for t =

0+, the NMOS transistor is on (VGS = +5 V) and the PMOS transistor is off

(VSG = 0 V), and the capacitor voltage begins to fall as C is discharged

through the NMOS transistor [3].